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4cd1a0be76
If there is a CMP.NZ that compares a single component (via a .zzzz
swizzle, for example) with 0, it can propagate its conditional modifier
back to a previous CMP that writes only that component. The specific
case that I saw was:
cmp.l.f0(8) g42<1>.xF g61<4>.xF (abs)g18<4>.zF
...
cmp.nz.f0(8) null<1>D g42<4>.xD 0D
In this case we can just delete the second CMP.
No changes on Broadwell or Skylake because they do not use the vec4
backend. Also no changes on GM45 or Iron Lake.
Sandy Bridge, Ivy Bridge, and Haswell had similar results. (Sandy Bridge shown)
total instructions in shared programs: 10856676 -> 10852569 (-0.04%)
instructions in affected programs: 228322 -> 224215 (-1.80%)
helped: 1331
HURT: 0
helped stats (abs) min: 1 max: 7 x̄: 3.09 x̃: 4
helped stats (rel) min: 0.11% max: 6.67% x̄: 1.88% x̃: 1.83%
95% mean confidence interval for instructions value: -3.19 -2.99
95% mean confidence interval for instructions %-change: -1.93% -1.83%
Instructions are helped.
total cycles in shared programs: 154788865 -> 154732047 (-0.04%)
cycles in affected programs: 2485892 -> 2429074 (-2.29%)
helped: 1097
HURT: 59
helped stats (abs) min: 2 max: 168 x̄: 51.96 x̃: 64
helped stats (rel) min: 0.12% max: 12.70% x̄: 3.44% x̃: 2.22%
HURT stats (abs) min: 2 max: 16 x̄: 3.02 x̃: 2
HURT stats (rel) min: 0.18% max: 0.83% x̄: 0.64% x̃: 0.71%
95% mean confidence interval for cycles value: -51.04 -47.26
95% mean confidence interval for cycles %-change: -3.40% -3.07%
Cycles are helped.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
365 lines
14 KiB
C++
365 lines
14 KiB
C++
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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/** @file brw_vec4_cmod_propagation.cpp
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*
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* Really similar to brw_fs_cmod_propagation but adapted to vec4 needs. Check
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* brw_fs_cmod_propagation for further details on the rationale behind this
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* optimization.
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*/
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#include "brw_vec4.h"
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#include "brw_cfg.h"
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#include "brw_eu.h"
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namespace brw {
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static bool
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writemasks_incompatible(const vec4_instruction *earlier,
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const vec4_instruction *later)
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{
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return (earlier->dst.writemask != WRITEMASK_X &&
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earlier->dst.writemask != WRITEMASK_XYZW) ||
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(earlier->dst.writemask == WRITEMASK_XYZW &&
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later->src[0].swizzle != BRW_SWIZZLE_XYZW) ||
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(later->dst.writemask & ~earlier->dst.writemask) != 0;
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}
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static bool
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opt_cmod_propagation_local(bblock_t *block, vec4_visitor *v)
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{
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bool progress = false;
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int ip = block->end_ip + 1;
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foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
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ip--;
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if ((inst->opcode != BRW_OPCODE_AND &&
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inst->opcode != BRW_OPCODE_CMP &&
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inst->opcode != BRW_OPCODE_MOV) ||
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inst->predicate != BRW_PREDICATE_NONE ||
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!inst->dst.is_null() ||
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(inst->src[0].file != VGRF && inst->src[0].file != ATTR &&
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inst->src[0].file != UNIFORM))
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continue;
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/* An ABS source modifier can only be handled when processing a compare
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* with a value other than zero.
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*/
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if (inst->src[0].abs &&
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(inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero()))
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continue;
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if (inst->opcode == BRW_OPCODE_AND &&
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!(inst->src[1].is_one() &&
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inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate))
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continue;
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if (inst->opcode == BRW_OPCODE_MOV &&
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inst->conditional_mod != BRW_CONDITIONAL_NZ)
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continue;
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bool read_flag = false;
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foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) {
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/* A CMP with a second source of zero can match with anything. A CMP
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* with a second source that is not zero can only match with an ADD
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* instruction.
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*/
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if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) {
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bool negate;
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if (scan_inst->opcode != BRW_OPCODE_ADD)
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goto not_match;
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if (writemasks_incompatible(scan_inst, inst))
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goto not_match;
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/* A CMP is basically a subtraction. The result of the
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* subtraction must be the same as the result of the addition.
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* This means that one of the operands must be negated. So (a +
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* b) vs (a == -b) or (a + -b) vs (a == b).
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*/
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if ((inst->src[0].equals(scan_inst->src[0]) &&
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inst->src[1].negative_equals(scan_inst->src[1])) ||
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(inst->src[0].equals(scan_inst->src[1]) &&
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inst->src[1].negative_equals(scan_inst->src[0]))) {
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negate = false;
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} else if ((inst->src[0].negative_equals(scan_inst->src[0]) &&
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inst->src[1].equals(scan_inst->src[1])) ||
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(inst->src[0].negative_equals(scan_inst->src[1]) &&
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inst->src[1].equals(scan_inst->src[0]))) {
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negate = true;
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} else {
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goto not_match;
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}
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if (scan_inst->exec_size != inst->exec_size ||
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scan_inst->group != inst->group)
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goto not_match;
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/* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*
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* So we don't have to bail if scan_inst has saturate.
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*/
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/* Otherwise, try propagating the conditional. */
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const enum brw_conditional_mod cond =
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negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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inst->remove(block);
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progress = true;
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}
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break;
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}
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if (regions_overlap(inst->src[0], inst->size_read(0),
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scan_inst->dst, scan_inst->size_written)) {
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if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) ||
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scan_inst->dst.offset != inst->src[0].offset ||
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scan_inst->exec_size != inst->exec_size ||
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scan_inst->group != inst->group) {
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break;
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}
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/* If scan_inst is a CMP that produces a single value and inst is
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* a CMP.NZ that consumes only that value, remove inst.
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*/
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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(inst->src[0].type == BRW_REGISTER_TYPE_D ||
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inst->src[0].type == BRW_REGISTER_TYPE_UD) &&
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(inst->opcode == BRW_OPCODE_CMP ||
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inst->opcode == BRW_OPCODE_MOV) &&
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scan_inst->opcode == BRW_OPCODE_CMP &&
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((inst->src[0].swizzle == BRW_SWIZZLE_XXXX &&
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scan_inst->dst.writemask == WRITEMASK_X) ||
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(inst->src[0].swizzle == BRW_SWIZZLE_YYYY &&
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scan_inst->dst.writemask == WRITEMASK_Y) ||
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(inst->src[0].swizzle == BRW_SWIZZLE_ZZZZ &&
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scan_inst->dst.writemask == WRITEMASK_Z) ||
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(inst->src[0].swizzle == BRW_SWIZZLE_WWWW &&
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scan_inst->dst.writemask == WRITEMASK_W))) {
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if (inst->dst.writemask != scan_inst->dst.writemask) {
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src_reg temp(v, glsl_type::vec4_type, 1);
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/* Given a sequence like:
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*
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* cmp.ge.f0(8) g21<1>.xF g20<4>.xF g18<4>.xF
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* ...
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* cmp.nz.f0(8) null<1>D g21<4>.xD 0D
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*
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* Replace it with something like:
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*
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* cmp.ge.f0(8) g22<1>F g20<4>.xF g18<4>.xF
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* mov(8) g21<1>.xF g22<1>.xxxxF
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*
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* The added MOV will most likely be removed later. In the
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* worst case, it should be cheaper to schedule.
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*/
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temp.swizzle = inst->src[0].swizzle;
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temp.type = scan_inst->src[0].type;
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vec4_instruction *mov = v->MOV(scan_inst->dst, temp);
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/* Modify the source swizzles on scan_inst. If scan_inst
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* was
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*
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* cmp.ge.f0(8) g21<1>.zF g20<4>.wzyxF g18<4>.yxwzF
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*
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* replace it with
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*
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* cmp.ge.f0(8) g21<1>.zF g20<4>.yyyyF g18<4>.wwwwF
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*/
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unsigned src0_chan;
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unsigned src1_chan;
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switch (scan_inst->dst.writemask) {
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case WRITEMASK_X:
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src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 0);
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src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 0);
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break;
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case WRITEMASK_Y:
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src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 1);
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src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 1);
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break;
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case WRITEMASK_Z:
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src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 2);
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src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 2);
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break;
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case WRITEMASK_W:
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src0_chan = BRW_GET_SWZ(scan_inst->src[0].swizzle, 3);
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src1_chan = BRW_GET_SWZ(scan_inst->src[1].swizzle, 3);
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break;
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default:
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unreachable("Impossible writemask");
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}
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scan_inst->src[0].swizzle = BRW_SWIZZLE4(src0_chan,
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src0_chan,
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src0_chan,
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src0_chan);
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/* There's no swizzle on immediate value sources. */
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if (scan_inst->src[1].file != IMM) {
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scan_inst->src[1].swizzle = BRW_SWIZZLE4(src1_chan,
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src1_chan,
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src1_chan,
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src1_chan);
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}
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scan_inst->dst = dst_reg(temp);
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scan_inst->dst.writemask = inst->dst.writemask;
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scan_inst->insert_after(block, mov);
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}
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inst->remove(block);
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progress = true;
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break;
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}
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if (writemasks_incompatible(scan_inst, inst))
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break;
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/* CMP's result is the same regardless of dest type. */
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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scan_inst->opcode == BRW_OPCODE_CMP &&
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(inst->dst.type == BRW_REGISTER_TYPE_D ||
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inst->dst.type == BRW_REGISTER_TYPE_UD)) {
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inst->remove(block);
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progress = true;
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break;
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}
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/* If the AND wasn't handled by the previous case, it isn't safe
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* to remove it.
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*/
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if (inst->opcode == BRW_OPCODE_AND)
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break;
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/* Comparisons operate differently for ints and floats */
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if (scan_inst->dst.type != inst->dst.type &&
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(scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
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inst->dst.type == BRW_REGISTER_TYPE_F))
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break;
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/* If the instruction generating inst's source also wrote the
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* flag, and inst is doing a simple .nz comparison, then inst
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* is redundant - the appropriate value is already in the flag
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* register. Delete inst.
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*/
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if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
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!inst->src[0].negate &&
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scan_inst->writes_flag()) {
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inst->remove(block);
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progress = true;
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break;
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}
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/* The conditional mod of the CMP/CMPN instructions behaves
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* specially because the flag output is not calculated from the
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* result of the instruction, but the other way around, which
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* means that even if the condmod to propagate and the condmod
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* from the CMP instruction are the same they will in general give
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* different results because they are evaluated based on different
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* inputs.
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*/
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if (scan_inst->opcode == BRW_OPCODE_CMP ||
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scan_inst->opcode == BRW_OPCODE_CMPN)
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break;
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/* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods":
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*
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* * Note that the [post condition signal] bits generated at
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* the output of a compute are before the .sat.
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*/
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if (scan_inst->saturate)
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break;
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/* From the Sky Lake PRM, Vol 2a, "Multiply":
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*
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* "When multiplying integer data types, if one of the sources
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* is a DW, the resulting full precision data is stored in
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* the accumulator. However, if the destination data type is
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* either W or DW, the low bits of the result are written to
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* the destination register and the remaining high bits are
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* discarded. This results in undefined Overflow and Sign
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* flags. Therefore, conditional modifiers and saturation
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* (.sat) cannot be used in this case.
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*
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* We just disallow cmod propagation on all integer multiplies.
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*/
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if (!brw_reg_type_is_floating_point(scan_inst->dst.type) &&
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scan_inst->opcode == BRW_OPCODE_MUL)
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break;
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/* Otherwise, try propagating the conditional. */
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enum brw_conditional_mod cond =
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inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
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: inst->conditional_mod;
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if (scan_inst->can_do_cmod() &&
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((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
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scan_inst->conditional_mod == cond)) {
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scan_inst->conditional_mod = cond;
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inst->remove(block);
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progress = true;
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}
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break;
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}
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not_match:
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if (scan_inst->writes_flag())
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break;
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read_flag = read_flag || scan_inst->reads_flag();
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}
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}
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return progress;
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}
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bool
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vec4_visitor::opt_cmod_propagation()
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{
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bool progress = false;
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foreach_block_reverse(block, cfg) {
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progress = opt_cmod_propagation_local(block, this) || progress;
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}
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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} /* namespace brw */
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