mirror of
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synced 2026-05-19 04:58:08 +02:00
15257b65c6
Via Coccinelle patch:
@@
@@
-nir_metadata_block_index | nir_metadata_dominance
+nir_metadata_control_flow
...plus some manual fixups for call sites missed by coccinelle.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Juan A. Suarez Romero <jasuarez@igalia.com> [broadcom]
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> [lima]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29745>
84 lines
3 KiB
C
84 lines
3 KiB
C
/*
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* Copyright © 2018 Intel Corporation
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* Copyright © 2018 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "v3d_compiler.h"
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#include "compiler/nir/nir_builder.h"
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#include "compiler/nir/nir_format_convert.h"
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/** @file v3d_nir_lower_scratch.c
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*
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* Swizzles around the addresses of
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* nir_intrinsic_load_scratch/nir_intrinsic_store_scratch so that a QPU stores
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* a cacheline at a time per dword of scratch access.
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*/
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static nir_def *
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v3d_nir_scratch_offset(nir_builder *b, nir_intrinsic_instr *instr)
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{
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b->cursor = nir_before_instr(&instr->instr);
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nir_def *offset = nir_get_io_offset_src(instr)->ssa;
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assert(nir_intrinsic_align_mul(instr) >= 4);
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assert(nir_intrinsic_align_offset(instr) % 4 == 0);
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/* The spill_offset register will already have the subgroup ID (EIDX)
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* shifted and ORed in at bit 2, so all we need to do is to move the
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* dword index up above V3D_CHANNELS.
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*/
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return nir_imul_imm(b, offset, V3D_CHANNELS);
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}
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static void
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v3d_nir_lower_scratch_instr(nir_builder *b, nir_intrinsic_instr *instr)
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{
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/* scalarized through nir_lower_mem_access_bit_sizes */
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assert(instr->num_components == 1);
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nir_def *offset = v3d_nir_scratch_offset(b, instr);
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nir_src_rewrite(nir_get_io_offset_src(instr), offset);
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}
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static bool
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v3d_nir_lower_scratch_cb(nir_builder *b,
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nir_intrinsic_instr *intr,
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void *_state)
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{
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switch (intr->intrinsic) {
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case nir_intrinsic_load_scratch:
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case nir_intrinsic_store_scratch:
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v3d_nir_lower_scratch_instr(b, intr);
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return true;
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default:
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return false;
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}
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return false;
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}
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bool
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v3d_nir_lower_scratch(nir_shader *s)
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{
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return nir_shader_intrinsics_pass(s, v3d_nir_lower_scratch_cb,
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nir_metadata_control_flow, NULL);
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}
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