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d09ad16fd4
The vast majority of AMD GPUs (except the very first GCN) have the same SDMA packet format, so let's just call it SDMA instead of CIK_SDMA. (And leave the oldest GPUs with SI_SDMA as they are now.) Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26110>
377 lines
21 KiB
C
377 lines
21 KiB
C
/*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef SID_H
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#define SID_H
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#include "amdgfxregs.h"
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/* si values */
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#define SI_CONFIG_REG_OFFSET 0x00008000
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#define SI_CONFIG_REG_END 0x0000B000
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#define SI_SH_REG_OFFSET 0x0000B000
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#define SI_SH_REG_END 0x0000C000
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#define SI_CONTEXT_REG_OFFSET 0x00028000
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#define SI_CONTEXT_REG_END 0x00030000
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#define CIK_UCONFIG_REG_OFFSET 0x00030000
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#define CIK_UCONFIG_REG_END 0x00040000
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#define SI_UCONFIG_PERF_REG_OFFSET 0x00034000
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#define SI_UCONFIG_PERF_REG_END 0x00038000
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/* For register shadowing: */
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#define SI_SH_REG_SPACE_SIZE (SI_SH_REG_END - SI_SH_REG_OFFSET)
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#define SI_CONTEXT_REG_SPACE_SIZE (SI_CONTEXT_REG_END - SI_CONTEXT_REG_OFFSET)
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#define SI_UCONFIG_REG_SPACE_SIZE (CIK_UCONFIG_REG_END - CIK_UCONFIG_REG_OFFSET)
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#define SI_UCONFIG_PERF_REG_SPACE_SIZE (SI_UCONFIG_PERF_REG_END - SI_UCONFIG_PERF_REG_OFFSET)
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#define SI_SHADOWED_SH_REG_OFFSET 0
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#define SI_SHADOWED_CONTEXT_REG_OFFSET SI_SH_REG_SPACE_SIZE
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#define SI_SHADOWED_UCONFIG_REG_OFFSET (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE)
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#define SI_SHADOWED_REG_BUFFER_SIZE \
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(SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + SI_UCONFIG_REG_SPACE_SIZE)
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/* All registers defined in this packet section don't exist and the only
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* purpose of these definitions is to define packet encoding that
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* the IB parser understands, and also to have an accurate documentation.
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*/
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#define PKT3_NOP 0x10
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#define PKT3_SET_BASE 0x11
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#define PKT3_CLEAR_STATE 0x12
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#define PKT3_INDEX_BUFFER_SIZE 0x13
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#define PKT3_DISPATCH_DIRECT 0x15
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#define PKT3_DISPATCH_INDIRECT 0x16
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#define PKT3_ATOMIC_MEM 0x1E
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#define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0)
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#define TC_OP_ATOMIC_SUB_32 0x10
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#define TC_OP_ATOMIC_CMPSWAP_32 0x48
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#define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8)
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#define ATOMIC_COMMAND_SINGLE_PASS 0x0
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#define ATOMIC_COMMAND_LOOP 0x1
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#define PKT3_OCCLUSION_QUERY 0x1F /* GFX7+ */
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#define PKT3_SET_PREDICATION 0x20
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#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8)
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#define PREDICATION_DRAW_VISIBLE (1 << 8)
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#define PREDICATION_HINT_WAIT (0 << 12)
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#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12)
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#define PRED_OP(x) ((x) << 16)
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#define PREDICATION_OP_CLEAR 0x0
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#define PREDICATION_OP_ZPASS 0x1
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#define PREDICATION_OP_PRIMCOUNT 0x2
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#define PREDICATION_OP_BOOL64 0x3
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#define PREDICATION_OP_BOOL32 0x4
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#define PREDICATION_CONTINUE (1 << 31)
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#define PKT3_COND_EXEC 0x22
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#define PKT3_PRED_EXEC 0x23
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#define PKT3_DRAW_INDIRECT 0x24
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#define PKT3_DRAW_INDEX_INDIRECT 0x25
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#define PKT3_INDEX_BASE 0x26
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#define PKT3_DRAW_INDEX_2 0x27
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#define PKT3_CONTEXT_CONTROL 0x28
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#define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0)
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#define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1)
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#define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15)
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#define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16)
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#define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24)
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#define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28)
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#define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31)
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#define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0)
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#define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1)
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#define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15)
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#define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16)
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#define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24)
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#define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31)
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#define PKT3_INDEX_TYPE 0x2A /* GFX6-8 */
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#define PKT3_DRAW_INDIRECT_MULTI 0x2C
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#define R_2C3_DRAW_INDEX_LOC 0x2C3
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#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30)
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#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31)
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#define PKT3_DRAW_INDEX_AUTO 0x2D
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#define PKT3_DRAW_INDEX_IMMD 0x2E /* GFX6 only */
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#define PKT3_NUM_INSTANCES 0x2F
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#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PKT3_INDIRECT_BUFFER_SI 0x32 /* GFX6 only */
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#define PKT3_INDIRECT_BUFFER_CONST 0x33
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#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
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#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
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#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x)&0x3) << 1)
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#define STRMOUT_OFFSET_FROM_PACKET 0
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#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
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#define STRMOUT_OFFSET_FROM_MEM 2
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#define STRMOUT_OFFSET_NONE 3
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#define STRMOUT_DATA_TYPE(x) (((unsigned)(x)&0x1) << 7)
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#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x)&0x3) << 8)
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#define PKT3_DRAW_INDEX_OFFSET_2 0x35
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#define PKT3_WRITE_DATA 0x37
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#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PKT3_MEM_SEMAPHORE 0x39
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#define PKT3_MPEG_INDEX 0x3A /* GFX6 only */
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#define PKT3_WAIT_REG_MEM 0x3C
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#define WAIT_REG_MEM_EQUAL 3
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#define WAIT_REG_MEM_NOT_EQUAL 4
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#define WAIT_REG_MEM_GREATER_OR_EQUAL 5
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#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4)
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#define WAIT_REG_MEM_PFP (1 << 8)
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#define PKT3_MEM_WRITE 0x3D /* GFX6 only */
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#define PKT3_INDIRECT_BUFFER 0x3F /* GFX6+ */
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#define PKT3_COPY_DATA 0x40
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#define COPY_DATA_SRC_SEL(x) ((x)&0xf)
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#define COPY_DATA_REG 0
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#define COPY_DATA_SRC_MEM 1 /* only valid as source */
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#define COPY_DATA_TC_L2 2
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#define COPY_DATA_GDS 3
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#define COPY_DATA_PERF 4
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#define COPY_DATA_IMM 5
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#define COPY_DATA_TIMESTAMP 9
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#define COPY_DATA_DST_SEL(x) (((unsigned)(x)&0xf) << 8)
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#define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */
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#define COPY_DATA_TC_L2 2
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#define COPY_DATA_GDS 3
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#define COPY_DATA_PERF 4
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#define COPY_DATA_DST_MEM 5
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#define COPY_DATA_COUNT_SEL (1 << 16)
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#define COPY_DATA_WR_CONFIRM (1 << 20)
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#define COPY_DATA_ENGINE_PFP (1 << 30)
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/* 1. header
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* 2. SRC_ADDR_LO [31:0] or DATA [31:0]
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* 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0]
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* 4. DST_ADDR_LO [31:0]
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* 5. DST_ADDR_HI [15:0]
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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#define PKT3_CP_DMA 0x41 /* GFX6 only */
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#define PKT3_PFP_SYNC_ME 0x42
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#define PKT3_SURFACE_SYNC 0x43 /* deprecated on GFX7, use ACQUIRE_MEM */
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#define PKT3_ME_INITIALIZE 0x44 /* GFX6 only */
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#define PKT3_COND_WRITE 0x45
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#define PKT3_EVENT_WRITE 0x46
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#define EVENT_TYPE(x) ((x) << 0)
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/* 0 - any non-TS event
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* 1 - ZPASS_DONE
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* 2 - SAMPLE_PIPELINESTAT
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* 3 - SAMPLE_STREAMOUTSTAT*
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* 4 - *S_PARTIAL_FLUSH
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* 5 - TS events
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*/
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#define EVENT_INDEX(x) ((x) << 8)
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#define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3)
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#define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9)
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/* 0 - 32 bits
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* 1 - 64 bits
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* 2 - 128 bits
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* 3 - 256 bits
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*/
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#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11)
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#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21)
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#define PKT3_EVENT_WRITE_EOP 0x47 /* GFX6-8 */
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/* EVENT_WRITE_EOP (GFX6-8) & RELEASE_MEM (GFX9) */
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#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12)
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#define EVENT_TC_VOL_ACTION_ENA (1 << 13)
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#define EVENT_TC_WB_ACTION_ENA (1 << 15)
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#define EVENT_TCL1_ACTION_ENA (1 << 16)
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#define EVENT_TC_ACTION_ENA (1 << 17)
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#define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */
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#define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */
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#define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */
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#define EOP_DST_SEL(x) ((x) << 16)
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#define EOP_DST_SEL_MEM 0
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#define EOP_DST_SEL_TC_L2 1
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#define EOP_INT_SEL(x) ((x) << 24)
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#define EOP_INT_SEL_NONE 0
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#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
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#define EOP_DATA_SEL(x) ((x) << 29)
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#define EOP_DATA_SEL_DISCARD 0
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#define EOP_DATA_SEL_VALUE_32BIT 1
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#define EOP_DATA_SEL_VALUE_64BIT 2
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#define EOP_DATA_SEL_TIMESTAMP 3
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#define EOP_DATA_SEL_GDS 5
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#define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16))
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#define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8 */
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#define EOS_DATA_SEL(x) ((x) << 29)
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#define EOS_DATA_SEL_APPEND_COUNT 0
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#define EOS_DATA_SEL_GDS 1
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#define EOS_DATA_SEL_VALUE_32BIT 2
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/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
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* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
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* DST_SEL=MC. Only GFX7 chips are affected.
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*/
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#define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8, breaks CP DMA */
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#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */
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/* 1. header
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* 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0]
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* 2. SRC_ADDR_LO [31:0] or DATA [31:0]
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* 3. SRC_ADDR_HI [31:0]
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* 4. DST_ADDR_LO [31:0]
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* 5. DST_ADDR_HI [31:0]
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* 6. COMMAND [29:22] | BYTE_COUNT [20:0]
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*/
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#define PKT3_DISPATCH_MESH_INDIRECT_MULTI 0x4C /* Indirect mesh shader only dispatch [GFX only], GFX10.3+ */
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#define S_4C1_XYZ_DIM_REG(x) ((x & 0xFFFF))
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#define S_4C1_DRAW_INDEX_REG(x) ((x & 0xFFFF) << 16)
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#define S_4C2_DRAW_INDEX_ENABLE(x) ((x & 1) << 31)
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#define S_4C2_COUNT_INDIRECT_ENABLE(x) ((x & 1) << 30)
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#define S_4C2_THREAD_TRACE_MARKER_ENABLE(x) ((x & 1) << 29)
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#define S_4C2_XYZ_DIM_ENABLE(x) ((x & 1) << 28) /* GFX11+ */
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#define S_4C2_MODE1_ENABLE(x) ((x & 1) << 27) /* GFX11+ */
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#define PKT3_DISPATCH_TASKMESH_GFX 0x4D /* Task + mesh shader dispatch [GFX side], GFX10.3+ */
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#define S_4D0_RING_ENTRY_REG(x) ((x & 0xFFFF) << 16)
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#define S_4D0_XYZ_DIM_REG(x) ((x & 0xFFFF))
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#define S_4D1_THREAD_TRACE_MARKER_ENABLE(x) ((x & 1) << 31)
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#define S_4D1_XYZ_DIM_ENABLE(x) ((x & 1) << 30) /* GFX11+ */
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#define S_4D1_MODE1_ENABLE(x) ((x & 1) << 29) /* GFX11+ */
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#define S_4D1_LINEAR_DISPATCH_ENABLE(x) ((x & 1) << 28) /* GFX11+ */
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#define PKT3_DISPATCH_MESH_DIRECT 0x4E /* Direct mesh shader only dispatch [GFX only], GFX11+ */
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#define PKT3_DMA_DATA 0x50 /* GFX7+ */
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#define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */
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#define PKT3_ONE_REG_WRITE 0x57 /* GFX6 only */
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#define PKT3_ACQUIRE_MEM 0x58 /* GFX7+ */
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#define PKT3_REWIND 0x59 /* GFX8+ [any ring] or GFX7 [compute ring only] */
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#define PKT3_PRIME_UTCL2 0x5D
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#define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */
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#define PKT3_LOAD_SH_REG 0x5F
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#define PKT3_LOAD_CONTEXT_REG 0x61
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#define PKT3_LOAD_SH_REG_INDEX 0x63 /* GFX8+ */
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#define PKT3_SET_CONFIG_REG 0x68
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#define PKT3_SET_CONTEXT_REG 0x69
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#define PKT3_SET_SH_REG 0x76
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#define PKT3_SET_SH_REG_OFFSET 0x77
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#define PKT3_SET_UCONFIG_REG 0x79 /* GFX7+ */
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#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */
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#define PKT3_LOAD_CONST_RAM 0x80
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#define PKT3_WRITE_CONST_RAM 0x81
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#define PKT3_DUMP_CONST_RAM 0x83
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#define PKT3_INCREMENT_CE_COUNTER 0x84
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#define PKT3_INCREMENT_DE_COUNTER 0x85
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#define PKT3_WAIT_ON_CE_COUNTER 0x86
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#define PKT3_SET_SH_REG_INDEX 0x9B
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#define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* GFX8+ */
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#define PKT3_DISPATCH_TASK_STATE_INIT 0xA9 /* Tells the HW about the task control buffer, GFX10.3+ */
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#define PKT3_DISPATCH_TASKMESH_DIRECT_ACE 0xAA /* Direct task + mesh shader dispatch [ACE side], GFX10.3+ */
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#define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task + mesh shader dispatch [ACE side], GFX10.3+ */
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#define S_AD2_RING_ENTRY_REG(x) ((x & 0xFFFF))
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#define S_AD3_COUNT_INDIRECT_ENABLE(x) ((x & 1) << 1)
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#define S_AD3_DRAW_INDEX_ENABLE(x) ((x & 1) << 2)
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#define S_AD3_XYZ_DIM_ENABLE(x) ((x & 1) << 3)
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#define S_AD3_DRAW_INDEX_REG(x) ((x & 0xFFFF) << 16)
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#define S_AD4_XYZ_DIM_REG(x) ((x & 0xFFFF))
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#define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */
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#define EVENT_WRITE_ZPASS_PFP_VERSION 1458
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/* Use these on GFX11 with a high PFP firmware version (only dGPUs should have that, not APUs)
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* because they are the fastest SET packets there.
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* SET_CONTEXT_REG_PAIRS_PACKED:
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* SET_SH_REG_PAIRS_PACKED:
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* SET_SH_REG_PAIRS_PACKED_N:
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* Format: header, count, (offset0 | (offset1 << 16), value0, value1)^(count / 2)
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* - "count" is the register count and must be aligned to 2.
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* - Consecutive offsets must not be equal.
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* - RESET_FILTER_CAM must be set to 1.
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* - If the register count is odd, write the first register again at the end to make it even.
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* - The SH_*_PACKED* variants require register shadowing to be enabled.
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* - The *_N variant is identical to the non-N variant, but the maximum allowed "count" is 14
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* and it's faster.
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*/
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#define PKT3_SET_CONTEXT_REG_PAIRS 0xB8 /* GFX11+, don't use */
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#define PKT3_SET_CONTEXT_REG_PAIRS_PACKED 0xB9 /* GFX11+ */
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#define PKT3_SET_SH_REG_PAIRS 0xBA /* GFX11+, don't use */
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#define PKT3_SET_SH_REG_PAIRS_PACKED 0xBB /* GFX11+ */
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#define PKT3_SET_SH_REG_PAIRS_PACKED_N 0xBD /* GFX11+ */
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#define PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30)
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#define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
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#define PKT_TYPE_C 0x3FFFFFFF
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#define PKT_COUNT_S(x) (((unsigned)(x)&0x3FFF) << 16)
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#define PKT_COUNT_G(x) (((x) >> 16) & 0x3FFF)
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#define PKT_COUNT_C 0xC000FFFF
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#define PKT3_IT_OPCODE_S(x) (((unsigned)(x)&0xFF) << 8)
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#define PKT3_IT_OPCODE_G(x) (((x) >> 8) & 0xFF)
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#define PKT3_IT_OPCODE_C 0xFFFF00FF
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#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
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#define PKT3_SHADER_TYPE_S(x) (((unsigned)(x) & 0x1) << 1)
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#define PKT3_SHADER_TYPE_G(x) (((x) >> 1) & 0x1)
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#define PKT3_RESET_FILTER_CAM_S(x) (((unsigned)(x) & 0x1) << 2)
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#define PKT3_RESET_FILTER_CAM_G(x) (((unsigned)(x) >> 2) & 0x1)
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#define PKT3(op, count, predicate) \
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(PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
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#define PKT2_NOP_PAD PKT_TYPE_S(2)
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#define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */
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/* SI async DMA packets */
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#define SI_DMA_PACKET(cmd, sub_cmd, n) \
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((((unsigned)(cmd)&0xF) << 28) | (((unsigned)(sub_cmd)&0xFF) << 20) | \
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(((unsigned)(n)&0xFFFFF) << 0))
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/* SI async DMA Packet types */
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#define SI_DMA_PACKET_WRITE 0x2
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#define SI_DMA_PACKET_COPY 0x3
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#define SI_DMA_COPY_MAX_BYTE_ALIGNED_SIZE 0xfffe0
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/* The documentation says 0xffff8 is the maximum size in dwords, which is
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* 0x3fffe0 in bytes. */
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#define SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE 0x3fffe0
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#define SI_DMA_COPY_DWORD_ALIGNED 0x00
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#define SI_DMA_COPY_BYTE_ALIGNED 0x40
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#define SI_DMA_COPY_TILED 0x8
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#define SI_DMA_PACKET_INDIRECT_BUFFER 0x4
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#define SI_DMA_PACKET_SEMAPHORE 0x5
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#define SI_DMA_PACKET_FENCE 0x6
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#define SI_DMA_PACKET_TRAP 0x7
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#define SI_DMA_PACKET_SRBM_WRITE 0x9
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#define SI_DMA_PACKET_CONSTANT_FILL 0xd
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#define SI_DMA_PACKET_NOP 0xf
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/* CIK async DMA packets */
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#define SDMA_PACKET(op, sub_op, n) \
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((((unsigned)(n)&0xFFFF) << 16) | (((unsigned)(sub_op)&0xFF) << 8) | \
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(((unsigned)(op)&0xFF) << 0))
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/* CIK async DMA packet types */
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#define SDMA_OPCODE_NOP 0x0
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#define SDMA_OPCODE_COPY 0x1
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#define SDMA_COPY_SUB_OPCODE_LINEAR 0x0
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#define SDMA_COPY_SUB_OPCODE_TILED 0x1
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#define SDMA_COPY_SUB_OPCODE_SOA 0x3
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#define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 0x4
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#define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 0x5
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#define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 0x6
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#define SDMA_OPCODE_WRITE 0x2
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#define SDMA_WRITE_SUB_OPCODE_LINEAR 0x0
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#define SDMA_WRITE_SUB_OPCODE_TILED 0x1
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#define SDMA_OPCODE_INDIRECT_BUFFER 0x4
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#define SDMA_OPCODE_FENCE 0x5
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#define SDMA_FENCE_MTYPE_UC 0x3
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#define SDMA_OPCODE_TRAP 0x6
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#define SDMA_OPCODE_SEMAPHORE 0x7
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#define SDMA_OPCODE_POLL_REGMEM 0x8
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#define SDMA_POLL_MEM (1 << 31)
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#define SDMA_POLL_INTERVAL_160_CLK 0xa
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#define SDMA_POLL_RETRY_INDEFINITELY 0xfff
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#define SDMA_OPCODE_CONSTANT_FILL 0xb
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#define SDMA_OPCODE_TIMESTAMP 0xd
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#define SDMA_TS_SUB_OPCODE_SET_LOCAL_TIMESTAMP 0x0
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#define SDMA_TS_SUB_OPCODE_GET_LOCAL_TIMESTAMP 0x1
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#define SDMA_TS_SUB_OPCODE_GET_GLOBAL_TIMESTAMP 0x2
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#define SDMA_OPCODE_SRBM_WRITE 0xe
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/* There is apparently an undocumented HW limitation that
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* prevents the HW from copying the last 255 bytes of (1 << 22) - 1
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*/
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#define SDMA_V2_0_COPY_MAX_BYTES 0x3fff00 /* almost 4 MB*/
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#define SDMA_V5_2_COPY_MAX_BYTES 0x3fffff00 /* almost 1 GB */
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#define SDMA_NOP_PAD SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) /* header-only version */
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enum amd_cmp_class_flags
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{
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S_NAN = 1 << 0, // Signaling NaN
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Q_NAN = 1 << 1, // Quiet NaN
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N_INFINITY = 1 << 2, // Negative infinity
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N_NORMAL = 1 << 3, // Negative normal
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N_SUBNORMAL = 1 << 4, // Negative subnormal
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N_ZERO = 1 << 5, // Negative zero
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P_ZERO = 1 << 6, // Positive zero
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P_SUBNORMAL = 1 << 7, // Positive subnormal
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P_NORMAL = 1 << 8, // Positive normal
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P_INFINITY = 1 << 9 // Positive infinity
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};
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#endif /* _SID_H */
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