mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-18 20:18:06 +02:00
95d2f009a9
This also includes RT, task shaders and DGC IES for compute. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36570>
440 lines
31 KiB
C
440 lines
31 KiB
C
/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_CS_H
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#define RADV_CS_H
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#include <assert.h>
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#include <stdint.h>
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#include <string.h>
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#include "radv_cmd_buffer.h"
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#include "radv_radeon_winsys.h"
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#include "radv_sdma.h"
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#include "sid.h"
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static inline unsigned
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radeon_check_space(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, unsigned needed)
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{
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assert(cs->cdw <= cs->reserved_dw);
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if (cs->max_dw - cs->cdw < needed)
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ws->cs_grow(cs, needed);
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cs->reserved_dw = MAX2(cs->reserved_dw, cs->cdw + needed);
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return cs->cdw + needed;
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}
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#define radeon_begin(cs) \
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struct radv_cmd_stream *__cs = (cs); \
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uint32_t __cs_num = __cs->b->cdw; \
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UNUSED uint32_t __cs_reserved_dw = __cs->b->reserved_dw; \
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UNUSED uint32_t *__cs_buf = __cs->b->buf
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#define radeon_end() \
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do { \
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__cs->b->cdw = __cs_num; \
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assert(__cs->b->cdw <= __cs->b->max_dw); \
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__cs = NULL; \
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} while (0)
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#define radeon_emit(value) \
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do { \
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assert(__cs_num < __cs_reserved_dw); \
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__cs_buf[__cs_num++] = (value); \
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} while (0)
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#define radeon_emit_array(values, num) \
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do { \
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unsigned __n = (num); \
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assert(__cs_num + __n <= __cs_reserved_dw); \
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memcpy(__cs_buf + __cs_num, (values), __n * 4); \
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__cs_num += __n; \
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} while (0)
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/* Packet building helpers. Don't use directly. */
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#define __radeon_set_reg_seq(reg, num, idx, prefix_name, packet, reset_filter_cam) \
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do { \
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assert((reg) >= prefix_name##_REG_OFFSET && (reg) < prefix_name##_REG_END); \
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radeon_emit(PKT3(packet, num, 0) | PKT3_RESET_FILTER_CAM_S(reset_filter_cam)); \
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radeon_emit((((reg) - prefix_name##_REG_OFFSET) >> 2) | ((idx) << 28)); \
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} while (0)
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#define __radeon_set_reg(reg, idx, value, prefix_name, packet) \
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do { \
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__radeon_set_reg_seq(reg, 1, idx, prefix_name, packet, 0); \
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radeon_emit(value); \
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} while (0)
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/* Packet building helpers for CONFIG registers. */
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#define radeon_set_config_reg_seq(reg, num) __radeon_set_reg_seq(reg, num, 0, SI_CONFIG, PKT3_SET_CONFIG_REG, 0)
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#define radeon_set_config_reg(reg, value) __radeon_set_reg(reg, 0, value, SI_CONFIG, PKT3_SET_CONFIG_REG)
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/* Packet building helpers for CONTEXT registers. */
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#define radeon_set_context_reg_seq(reg, num) __radeon_set_reg_seq(reg, num, 0, SI_CONTEXT, PKT3_SET_CONTEXT_REG, 0)
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#define radeon_set_context_reg(reg, value) __radeon_set_reg(reg, 0, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
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#define radeon_set_context_reg_idx(reg, idx, value) __radeon_set_reg(reg, idx, value, SI_CONTEXT, PKT3_SET_CONTEXT_REG)
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#define radeon_opt_set_context_reg(reg, reg_enum, value) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __value = (value); \
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if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
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__tracked_regs->reg_value[(reg_enum)] != __value) { \
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radeon_set_context_reg(reg, __value); \
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BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \
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__tracked_regs->reg_value[(reg_enum)] = __value; \
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__cs->context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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#define radeon_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __v1 = (v1), __v2 = (v2); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
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radeon_set_context_reg_seq(reg, 2); \
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radeon_emit(__v1); \
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radeon_emit(__v2); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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__cs->context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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#define radeon_opt_set_context_reg3(reg, reg_enum, v1, v2, v3) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2, 0x7) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
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__tracked_regs->reg_value[(reg_enum) + 2] != __v3) { \
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radeon_set_context_reg_seq(reg, 3); \
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radeon_emit(__v1); \
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radeon_emit(__v2); \
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radeon_emit(__v3); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 2); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
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__cs->context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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#define radeon_opt_set_context_reg4(reg, reg_enum, v1, v2, v3, v4) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __v1 = (v1), __v2 = (v2), __v3 = (v3), __v4 = (v4); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3, 0xf) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2 || \
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__tracked_regs->reg_value[(reg_enum) + 2] != __v3 || __tracked_regs->reg_value[(reg_enum) + 3] != __v4) { \
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radeon_set_context_reg_seq(reg, 4); \
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radeon_emit(__v1); \
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radeon_emit(__v2); \
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radeon_emit(__v3); \
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radeon_emit(__v4); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 3); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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__tracked_regs->reg_value[(reg_enum) + 2] = __v3; \
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__tracked_regs->reg_value[(reg_enum) + 3] = __v4; \
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__cs->context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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#define radeon_opt_set_context_regn(reg, values, saved_values, num) \
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do { \
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if (memcmp(values, saved_values, sizeof(uint32_t) * (num))) { \
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radeon_set_context_reg_seq(reg, num); \
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radeon_emit_array(values, num); \
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memcpy(saved_values, values, sizeof(uint32_t) * (num)); \
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__cs->context_roll_without_scissor_emitted = true; \
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} \
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} while (0)
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/* Packet building helpers for SH registers. */
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#define radeon_set_sh_reg_seq(reg, num) __radeon_set_reg_seq(reg, num, 0, SI_SH, PKT3_SET_SH_REG, 0)
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#define radeon_set_sh_reg(reg, value) __radeon_set_reg(reg, 0, value, SI_SH, PKT3_SET_SH_REG)
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#define radeon_set_sh_reg_idx(info, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_SH_REG_INDEX; \
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if ((info)->gfx_level < GFX10) \
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__opcode = PKT3_SET_SH_REG; \
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__radeon_set_reg(reg, idx, value, SI_SH, __opcode); \
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} while (0)
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/* Packet building helpers for UCONFIG registers. */
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#define radeon_set_uconfig_reg_seq(reg, num) __radeon_set_reg_seq(reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, 0)
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#define radeon_set_uconfig_reg(reg, value) __radeon_set_reg(reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
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#define radeon_set_uconfig_reg_idx(info, reg, idx, value) \
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do { \
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assert((idx)); \
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unsigned __opcode = PKT3_SET_UCONFIG_REG_INDEX; \
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if ((info)->gfx_level < GFX9 || ((info)->gfx_level == GFX9 && (info)->me_fw_version < 26)) \
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__opcode = PKT3_SET_UCONFIG_REG; \
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__radeon_set_reg(reg, idx, value, CIK_UCONFIG, __opcode); \
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} while (0)
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/*
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* On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM),
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* that means that it can skip register writes due to not taking correctly into account the
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* fields from the GRBM_GFX_INDEX. With this bit we can force the write.
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*/
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#define radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, reg, num) \
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do { \
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const bool __filter_cam_workaround = (gfx_level) >= GFX10 && (ring) == AMD_IP_GFX; \
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__radeon_set_reg_seq(reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, __filter_cam_workaround); \
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} while (0)
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#define radeon_set_uconfig_perfctr_reg(gfx_level, ring, reg, value) \
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do { \
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radeon_set_uconfig_perfctr_reg_seq(gfx_level, ring, reg, 1); \
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radeon_emit(value); \
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} while (0)
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#define radeon_set_privileged_config_reg(reg, value) \
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do { \
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assert((reg) < CIK_UCONFIG_REG_OFFSET); \
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radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); \
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radeon_emit(COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_PERF)); \
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radeon_emit(value); \
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radeon_emit(0); /* unused */ \
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radeon_emit((reg) >> 2); \
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radeon_emit(0); /* unused */ \
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} while (0)
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#define radeon_event_write_predicate(event_type, predicate) \
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do { \
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unsigned __event_type = (event_type); \
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radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, predicate)); \
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radeon_emit(EVENT_TYPE(__event_type) | EVENT_INDEX(__event_type == V_028A90_VS_PARTIAL_FLUSH || \
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__event_type == V_028A90_PS_PARTIAL_FLUSH || \
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__event_type == V_028A90_CS_PARTIAL_FLUSH \
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? 4 \
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: 0)); \
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} while (0)
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#define radeon_event_write(event_type) radeon_event_write_predicate(event_type, false)
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#define radeon_emit_32bit_pointer(sh_offset, va, info) \
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do { \
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assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \
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radeon_set_sh_reg(sh_offset, va); \
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} while (0)
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#define radeon_emit_64bit_pointer(sh_offset, va) \
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do { \
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radeon_set_sh_reg_seq(sh_offset, 2); \
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radeon_emit(va); \
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radeon_emit(va >> 32); \
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} while (0)
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/* GFX12 generic packet building helpers for PAIRS packets. Don't use these directly. */
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/* Reserved 1 DWORD to emit the packet header when the sequence ends. */
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#define __gfx12_begin_regs(header) uint32_t header = __cs_num++
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/* Set a register unconditionally. */
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#define __gfx12_set_reg(reg, value, base_offset) \
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do { \
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radeon_emit(((reg) - (base_offset)) >> 2); \
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radeon_emit(value); \
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} while (0)
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/* Set 1 context register optimally. */
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#define __gfx12_opt_set_reg(reg, reg_enum, value, base_offset) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __value = (value); \
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if (!BITSET_TEST(__tracked_regs->reg_saved_mask, (reg_enum)) || \
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__tracked_regs->reg_value[(reg_enum)] != __value) { \
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__gfx12_set_reg((reg), __value, base_offset); \
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BITSET_SET(__tracked_regs->reg_saved_mask, (reg_enum)); \
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__tracked_regs->reg_value[(reg_enum)] = __value; \
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} \
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} while (0)
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/* Set 2 context registers optimally. */
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#define __gfx12_opt_set_reg2(reg, reg_enum, v1, v2, base_offset) \
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do { \
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struct radv_tracked_regs *__tracked_regs = &__cs->tracked_regs; \
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const uint32_t __v1 = (v1), __v2 = (v2); \
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if (!BITSET_TEST_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1, 0x3) || \
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__tracked_regs->reg_value[(reg_enum)] != __v1 || __tracked_regs->reg_value[(reg_enum) + 1] != __v2) { \
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__gfx12_set_reg((reg), __v1, base_offset); \
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__gfx12_set_reg((reg) + 4, __v2, base_offset); \
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BITSET_SET_RANGE_INSIDE_WORD(__tracked_regs->reg_saved_mask, (reg_enum), (reg_enum) + 1); \
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__tracked_regs->reg_value[(reg_enum)] = __v1; \
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__tracked_regs->reg_value[(reg_enum) + 1] = __v2; \
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} \
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} while (0)
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/* End the sequence and emit the packet header. */
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#define __gfx12_end_regs(header, packet) \
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do { \
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if ((header) + 1 == __cs_num) { \
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__cs_num--; /* no registers have been set, back off */ \
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} else { \
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unsigned __dw_count = __cs_num - (header) - 2; \
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__cs_buf[(header)] = PKT3((packet), __dw_count, 0) | PKT3_RESET_FILTER_CAM_S(1); \
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} \
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} while (0)
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/* GFX12 generic packet building helpers for buffered registers. Don't use these directly. */
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#define __gfx12_push_reg(reg, value, base_offset) \
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do { \
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unsigned __i = __cs->num_buffered_sh_regs++; \
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assert(__i < ARRAY_SIZE(__cs->gfx12.buffered_sh_regs)); \
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__cs->gfx12.buffered_sh_regs[__i].reg_offset = ((reg) - (base_offset)) >> 2; \
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__cs->gfx12.buffered_sh_regs[__i].reg_value = value; \
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} while (0)
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/* GFX12 packet building helpers for PAIRS packets. */
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#define gfx12_begin_context_regs() __gfx12_begin_regs(__cs_context_reg_header)
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#define gfx12_set_context_reg(reg, value) __gfx12_set_reg(reg, value, SI_CONTEXT_REG_OFFSET)
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#define gfx12_opt_set_context_reg(reg, reg_enum, value) __gfx12_opt_set_reg(reg, reg_enum, value, SI_CONTEXT_REG_OFFSET)
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#define gfx12_opt_set_context_reg2(reg, reg_enum, v1, v2) \
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__gfx12_opt_set_reg2(reg, reg_enum, v1, v2, SI_CONTEXT_REG_OFFSET)
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#define gfx12_end_context_regs() __gfx12_end_regs(__cs_context_reg_header, PKT3_SET_CONTEXT_REG_PAIRS)
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/* GFX12 packet building helpers for buffered registers. */
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#define gfx12_push_sh_reg(reg, value) __gfx12_push_reg(reg, value, SI_SH_REG_OFFSET)
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#define gfx12_push_32bit_pointer(sh_offset, va, info) \
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do { \
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assert((va) == 0 || ((va) >> 32) == (info)->address32_hi); \
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gfx12_push_sh_reg(sh_offset, va); \
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} while (0)
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#define gfx12_push_64bit_pointer(sh_offset, va) \
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do { \
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gfx12_push_sh_reg(sh_offset, va); \
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gfx12_push_sh_reg(sh_offset + 4, va >> 32); \
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} while (0)
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ALWAYS_INLINE static void
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radv_gfx12_emit_buffered_regs(struct radv_device *device, struct radv_cmd_stream *cs)
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{
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const uint32_t reg_count = cs->num_buffered_sh_regs;
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if (!reg_count)
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return;
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radeon_check_space(device->ws, cs->b, 1 + reg_count * 2);
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_SET_SH_REG_PAIRS, reg_count * 2 - 1, 0) | PKT3_RESET_FILTER_CAM_S(1));
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radeon_emit_array(cs->gfx12.buffered_sh_regs, reg_count * 2);
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radeon_end();
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cs->num_buffered_sh_regs = 0;
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}
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ALWAYS_INLINE static void
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radv_cp_wait_mem(struct radv_cmd_stream *cs, const enum radv_queue_family qf, const uint32_t op, const uint64_t va,
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const uint32_t ref, const uint32_t mask)
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{
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assert(op == WAIT_REG_MEM_EQUAL || op == WAIT_REG_MEM_NOT_EQUAL || op == WAIT_REG_MEM_GREATER_OR_EQUAL);
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if (qf == RADV_QUEUE_GENERAL || qf == RADV_QUEUE_COMPUTE) {
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, false));
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radeon_emit(op | WAIT_REG_MEM_MEM_SPACE(1));
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radeon_emit(va);
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radeon_emit(va >> 32);
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radeon_emit(ref); /* reference value */
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radeon_emit(mask); /* mask */
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radeon_emit(4); /* poll interval */
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radeon_end();
|
|
} else if (qf == RADV_QUEUE_TRANSFER) {
|
|
radv_sdma_emit_wait_mem(cs, op, va, ref, mask);
|
|
} else {
|
|
UNREACHABLE("unsupported queue family");
|
|
}
|
|
}
|
|
|
|
ALWAYS_INLINE static unsigned
|
|
radv_cs_write_data_head(const struct radv_device *device, struct radv_cmd_stream *cs, const enum radv_queue_family qf,
|
|
const unsigned engine_sel, const uint64_t va, const unsigned count, const bool predicating)
|
|
{
|
|
/* Return the correct cdw at the end of the packet so the caller can assert it. */
|
|
const unsigned cdw_end = radeon_check_space(device->ws, cs->b, 4 + count);
|
|
|
|
if (qf == RADV_QUEUE_GENERAL || qf == RADV_QUEUE_COMPUTE) {
|
|
radeon_begin(cs);
|
|
radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + count, predicating));
|
|
radeon_emit(S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
|
|
radeon_emit(va);
|
|
radeon_emit(va >> 32);
|
|
radeon_end();
|
|
} else if (qf == RADV_QUEUE_TRANSFER) {
|
|
radv_sdma_emit_write_data_head(cs, va, count);
|
|
} else {
|
|
UNREACHABLE("unsupported queue family");
|
|
}
|
|
|
|
return cdw_end;
|
|
}
|
|
|
|
ALWAYS_INLINE static void
|
|
radv_cs_write_data(const struct radv_device *device, struct radv_cmd_stream *cs, const enum radv_queue_family qf,
|
|
const unsigned engine_sel, const uint64_t va, const unsigned count, const uint32_t *dwords,
|
|
const bool predicating)
|
|
{
|
|
ASSERTED const unsigned cdw_end = radv_cs_write_data_head(device, cs, qf, engine_sel, va, count, predicating);
|
|
|
|
radeon_begin(cs);
|
|
radeon_emit_array(dwords, count);
|
|
radeon_end();
|
|
assert(cs->b->cdw == cdw_end);
|
|
}
|
|
|
|
void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf,
|
|
unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel,
|
|
uint64_t va, uint32_t new_fence, uint64_t gfx9_eop_bug_va);
|
|
|
|
void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level,
|
|
uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf,
|
|
enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits,
|
|
uint64_t gfx9_eop_bug_va);
|
|
|
|
void radv_emit_cond_exec(const struct radv_device *device, struct radv_cmd_stream *cs, uint64_t va, uint32_t count);
|
|
|
|
void radv_cs_write_data_imm(struct radv_cmd_stream *cs, unsigned engine_sel, uint64_t va, uint32_t imm);
|
|
|
|
static inline void
|
|
radv_emit_pm4_commands(struct radv_cmd_stream *cs, const struct ac_pm4_state *pm4)
|
|
{
|
|
radeon_begin(cs);
|
|
radeon_emit_array(pm4->pm4, pm4->ndw);
|
|
radeon_end();
|
|
}
|
|
|
|
VkResult radv_create_cmd_stream(const struct radv_device *device, enum radv_queue_family family, bool is_secondary,
|
|
struct radv_cmd_stream **cs_out);
|
|
|
|
void radv_init_cmd_stream(struct radv_cmd_stream *cs);
|
|
|
|
void radv_reset_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
|
|
|
|
VkResult radv_finalize_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
|
|
|
|
void radv_destroy_cmd_stream(const struct radv_device *device, struct radv_cmd_stream *cs);
|
|
|
|
#endif /* RADV_CS_H */
|