mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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889c3ee6b8
Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21758>
352 lines
12 KiB
C
352 lines
12 KiB
C
/*
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* Copyright © 2022 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_private.h"
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#include "compiler/brw_compiler.h"
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#include "compiler/brw_nir.h"
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#include "compiler/spirv/nir_spirv.h"
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#include "dev/intel_debug.h"
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#include "util/macros.h"
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#include "anv_generated_indirect_draws.h"
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#include "shaders/gfx9_generated_draws_spv.h"
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#include "shaders/gfx11_generated_draws_spv.h"
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/* This pass takes vulkan descriptor bindings 0 & 1 and turns them into global
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* 64bit addresses. Binding 2 is left UBO that would normally be accessed
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* through the binding table but it fully promoted to push constants.
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*
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* As a result we're not using the binding table at all which is nice because
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* of the side command buffer we use for the generating shader does not
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* interact with the binding table allocation.
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*/
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static bool
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lower_vulkan_descriptors_instr(nir_builder *b, nir_instr *instr, void *cb_data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic != nir_intrinsic_load_vulkan_descriptor)
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return false;
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nir_instr *res_index_instr = intrin->src[0].ssa->parent_instr;
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assert(res_index_instr->type == nir_instr_type_intrinsic);
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nir_intrinsic_instr *res_index_intrin =
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nir_instr_as_intrinsic(res_index_instr);
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assert(res_index_intrin->intrinsic == nir_intrinsic_vulkan_resource_index);
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b->cursor = nir_after_instr(instr);
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nir_ssa_def *desc_value = NULL;
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switch (nir_intrinsic_binding(res_index_intrin)) {
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case 0: {
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desc_value =
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nir_load_ubo(b, 1, 64,
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nir_imm_int(b, 2),
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nir_imm_int(b,
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offsetof(struct anv_generated_indirect_params,
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indirect_data_addr)),
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.align_mul = 8,
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.align_offset = 0,
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.range_base = 0,
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.range = ~0);
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desc_value =
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nir_vec4(b,
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nir_unpack_64_2x32_split_x(b, desc_value),
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nir_unpack_64_2x32_split_y(b, desc_value),
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nir_imm_int(b, 0),
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nir_imm_int(b, 0));
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break;
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}
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case 1: {
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desc_value =
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nir_load_ubo(b, 1, 64,
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nir_imm_int(b, 2),
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nir_imm_int(b,
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offsetof(struct anv_generated_indirect_params,
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generated_cmds_addr)),
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.align_mul = 8,
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.align_offset = 0,
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.range_base = 0,
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.range = ~0);
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desc_value =
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nir_vec4(b,
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nir_unpack_64_2x32_split_x(b, desc_value),
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nir_unpack_64_2x32_split_y(b, desc_value),
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nir_imm_int(b, 0),
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nir_imm_int(b, 0));
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break;
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}
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case 2: {
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desc_value =
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nir_load_ubo(b, 1, 64,
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nir_imm_int(b, 2),
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nir_imm_int(b,
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offsetof(struct anv_generated_indirect_params,
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draw_ids_addr)),
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.align_mul = 8,
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.align_offset = 0,
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.range_base = 0,
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.range = ~0);
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desc_value =
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nir_vec4(b,
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nir_unpack_64_2x32_split_x(b, desc_value),
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nir_unpack_64_2x32_split_y(b, desc_value),
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nir_imm_int(b, 0),
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nir_imm_int(b, 0));
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break;
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}
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case 3:
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desc_value =
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nir_vec2(b,
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nir_imm_int(b, 2),
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nir_imm_int(b, 0));
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break;
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}
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, desc_value);
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return true;
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}
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static bool
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lower_vulkan_descriptors(nir_shader *shader)
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{
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return nir_shader_instructions_pass(shader,
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lower_vulkan_descriptors_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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static struct anv_shader_bin *
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compile_upload_spirv(struct anv_device *device,
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const void *key,
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uint32_t key_size,
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const uint32_t *spirv_source,
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uint32_t spirv_source_size,
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uint32_t sends_count_expectation)
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{
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struct spirv_to_nir_options spirv_options = {
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.caps = {
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.int64 = true,
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},
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.ubo_addr_format = nir_address_format_32bit_index_offset,
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.ssbo_addr_format = nir_address_format_64bit_global_32bit_offset,
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.environment = NIR_SPIRV_VULKAN,
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.create_library = false,
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};
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const nir_shader_compiler_options *nir_options =
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device->physical->compiler->nir_options[MESA_SHADER_FRAGMENT];
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nir_shader* nir =
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spirv_to_nir(spirv_source, spirv_source_size,
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NULL, 0, MESA_SHADER_FRAGMENT, "main",
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&spirv_options, nir_options);
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assert(nir != NULL);
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nir->info.internal = true;
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nir_validate_shader(nir, "after spirv_to_nir");
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nir_validate_ssa_dominance(nir, "after spirv_to_nir");
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NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
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NIR_PASS_V(nir, nir_lower_returns);
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NIR_PASS_V(nir, nir_inline_functions);
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NIR_PASS_V(nir, nir_opt_deref);
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/* Pick off the single entrypoint that we want */
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nir_remove_non_entrypoints(nir);
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NIR_PASS_V(nir, nir_lower_vars_to_ssa);
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NIR_PASS_V(nir, nir_copy_prop);
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NIR_PASS_V(nir, nir_opt_dce);
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NIR_PASS_V(nir, nir_opt_cse);
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NIR_PASS_V(nir, nir_opt_gcm, true);
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NIR_PASS_V(nir, nir_opt_peephole_select, 1, false, false);
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NIR_PASS_V(nir, nir_opt_dce);
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NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
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NIR_PASS_V(nir, nir_split_var_copies);
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NIR_PASS_V(nir, nir_split_per_member_structs);
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struct brw_compiler *compiler = device->physical->compiler;
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struct brw_nir_compiler_opts opts = {};
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brw_preprocess_nir(compiler, nir, &opts);
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NIR_PASS_V(nir, nir_propagate_invariant, false);
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NIR_PASS_V(nir, nir_lower_input_attachments,
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&(nir_input_attachment_options) {
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.use_fragcoord_sysval = true,
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.use_layer_id_sysval = true,
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});
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nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
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/* Do vectorizing here. For some reason when trying to do it in the back
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* this just isn't working.
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*/
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nir_load_store_vectorize_options options = {
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.modes = nir_var_mem_ubo | nir_var_mem_ssbo,
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.callback = brw_nir_should_vectorize_mem,
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.robust_modes = (nir_variable_mode)0,
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};
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NIR_PASS_V(nir, nir_opt_load_store_vectorize, &options);
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NIR_PASS_V(nir, lower_vulkan_descriptors);
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NIR_PASS_V(nir, nir_opt_dce);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo,
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nir_address_format_32bit_index_offset);
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NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ssbo,
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nir_address_format_64bit_global_32bit_offset);
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NIR_PASS_V(nir, nir_copy_prop);
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NIR_PASS_V(nir, nir_opt_constant_folding);
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NIR_PASS_V(nir, nir_opt_dce);
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struct brw_wm_prog_key wm_key;
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memset(&wm_key, 0, sizeof(wm_key));
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struct brw_wm_prog_data wm_prog_data = {
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.base.nr_params = nir->num_uniforms / 4,
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};
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brw_nir_analyze_ubo_ranges(compiler, nir, NULL, wm_prog_data.base.ubo_ranges);
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struct brw_compile_stats stats[3];
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struct brw_compile_fs_params params = {
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.nir = nir,
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.key = &wm_key,
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.prog_data = &wm_prog_data,
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.stats = stats,
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.log_data = device,
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.debug_flag = DEBUG_WM,
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};
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const unsigned *program = brw_compile_fs(compiler, nir, ¶ms);
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unsigned stat_idx = 0;
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if (wm_prog_data.dispatch_8) {
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assert(stats[stat_idx].spills == 0);
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assert(stats[stat_idx].fills == 0);
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assert(stats[stat_idx].sends == sends_count_expectation);
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stat_idx++;
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}
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if (wm_prog_data.dispatch_16) {
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assert(stats[stat_idx].spills == 0);
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assert(stats[stat_idx].fills == 0);
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assert(stats[stat_idx].sends == sends_count_expectation);
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stat_idx++;
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}
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if (wm_prog_data.dispatch_32) {
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assert(stats[stat_idx].spills == 0);
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assert(stats[stat_idx].fills == 0);
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assert(stats[stat_idx].sends == sends_count_expectation * 2);
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stat_idx++;
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}
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struct anv_pipeline_bind_map bind_map;
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memset(&bind_map, 0, sizeof(bind_map));
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struct anv_push_descriptor_info push_desc_info = {};
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struct anv_shader_bin *kernel =
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anv_device_upload_kernel(device,
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device->internal_cache,
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nir->info.stage,
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key, key_size, program,
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wm_prog_data.base.program_size,
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&wm_prog_data.base, sizeof(wm_prog_data),
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NULL, 0, NULL, &bind_map,
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&push_desc_info);
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ralloc_free(nir);
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return kernel;
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}
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VkResult
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anv_device_init_generated_indirect_draws(struct anv_device *device)
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{
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const struct intel_l3_weights w =
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intel_get_default_l3_weights(device->info,
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true /* wants_dc_cache */,
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false /* needs_slm */);
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device->generated_draw_l3_config = intel_get_l3_config(device->info, w);
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struct {
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char name[40];
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} indirect_draws_key = {
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.name = "anv-generated-indirect-draws",
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};
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device->generated_draw_kernel =
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anv_device_search_for_kernel(device,
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device->internal_cache,
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&indirect_draws_key,
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sizeof(indirect_draws_key),
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NULL);
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if (device->generated_draw_kernel == NULL) {
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const uint32_t *spirv_source =
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device->info->ver >= 11 ?
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gfx11_generated_draws_spv_source :
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gfx9_generated_draws_spv_source;
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const uint32_t spirv_source_size =
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device->info->ver >= 11 ?
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ARRAY_SIZE(gfx11_generated_draws_spv_source) :
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ARRAY_SIZE(gfx9_generated_draws_spv_source);
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const uint32_t send_count =
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device->info->ver >= 11 ?
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11 /* 2 * (2 loads + 3 stores) + 1 store */ :
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17 /* 2 * (2 loads + 6 stores) + 1 store */;
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device->generated_draw_kernel =
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compile_upload_spirv(device,
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&indirect_draws_key,
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sizeof(indirect_draws_key),
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spirv_source, spirv_source_size, send_count);
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}
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if (device->generated_draw_kernel == NULL)
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return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
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/* The cache already has a reference and it's not going anywhere so there
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* is no need to hold a second reference.
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*/
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anv_shader_bin_unref(device, device->generated_draw_kernel);
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return VK_SUCCESS;
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}
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void
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anv_device_finish_generated_indirect_draws(struct anv_device *device)
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{
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}
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