Qiang Yu 5d05ae5df0 aco: add tcs end regs for epilog usage ... Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24442>		2023-08-16 02:27:45 +00:00
..
addrlib	ac/radv: decouple radv vulkan driver and compiler from gallium	2023-08-03 09:45:42 +00:00
ci	ci/amd: add glx@glx-visuals-depth flake to raven	2023-08-12 13:35:23 +02:00
common	nir: s/nir_instr_ssa_def/nir_instr_def/	2023-08-15 17:44:27 +00:00
compiler	aco: add tcs end regs for epilog usage	2023-08-16 02:27:45 +00:00
drm-shim	amd/drm-shim: use fixed-width types	2023-06-23 18:35:52 +00:00
llvm	nir: Rename nir_instr_type_ssa_undef to nir_instr_type_undef	2023-08-15 17:44:27 +00:00
registers	ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MIT	2023-05-24 21:48:19 +00:00
vulkan	nir: s/nir_instr_ssa_def/nir_instr_def/	2023-08-15 17:44:27 +00:00
meson.build	meson: build radeonsi with aco	2023-05-15 02:01:10 +00:00