Zan Dobersek e30c329026 ir3: improve validation, display for ldp instructions ... During validation, an ldp instruction should have all its three source registers validated. For display, the half-type register name should be displayed when applicable. Signed-off-by: Zan Dobersek <zdobersek@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29875>		2024-08-07 14:32:28 +00:00
..
encode.c	isaspec: encode: Constify encode.type	2024-03-05 07:29:08 +00:00
ir3-cat0.xml	ir3: model predt/predf without sources	2024-04-23 19:18:29 +00:00
ir3-cat1.xml	freedreno/ir3: mova has special meaning for (r) flag	2024-06-18 16:52:31 +00:00
ir3-cat2.xml	ir3: Add support for (dis)assembling flat.b	2021-11-04 02:59:28 +00:00
ir3-cat3.xml	ir3/a7xx: Add definitions for (last) src GPR attribute	2023-04-27 21:06:47 +00:00
ir3-cat4.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
ir3-cat5.xml	ir3: add encoding for isam.v	2024-06-14 17:12:59 +00:00
ir3-cat6.xml	ir3: improve validation, display for ldp instructions	2024-08-07 14:32:28 +00:00
ir3-cat7.xml	ir3/a7xx: Add ccinv instruction	2023-09-05 16:19:30 +00:00
ir3-common.xml	ir3: rework TYPE_S8 as TYPE_U8_32	2024-07-03 08:31:39 +00:00
ir3-disasm.c	ir3-disasm: add option to disassemble hex number	2024-04-04 19:37:25 +00:00
ir3.xml	freedreno/isa: Convert to srcs/dsts	2021-06-23 17:20:29 +00:00
isa.h	isaspec: Move isa_decode(..) declaration	2022-09-03 19:26:04 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00