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1de44b1951
Lowering/layout is pretty much the same as direct descriptors. The caveats is that since the descriptor buffers are not visible from the binding tables we can't promote anything to the binding table (except push descriptors). The reason for this is that there is nothing that prevents an application to use both types of descriptors and because descriptor buffers have visible address + capture replay, we can't merge the 2 types in the same virtual address space location (limited to 4Gb max, limited 2Gb with binding tables). If we had the guarantee that both are not going to be used at the same time, we could consider a 2Gb VA for descriptor buffers. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
362 lines
15 KiB
C
362 lines
15 KiB
C
/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_nir.h"
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#include "nir_builder.h"
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#include "compiler/brw_nir.h"
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#include "util/mesa-sha1.h"
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#define sizeof_field(type, field) sizeof(((type *)0)->field)
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void
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anv_nir_compute_push_layout(nir_shader *nir,
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const struct anv_physical_device *pdevice,
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enum brw_robustness_flags robust_flags,
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bool fragment_dynamic,
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map,
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const struct anv_pipeline_push_map *push_map,
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enum anv_descriptor_set_layout_type desc_type,
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void *mem_ctx)
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{
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const struct brw_compiler *compiler = pdevice->compiler;
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const struct intel_device_info *devinfo = compiler->devinfo;
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memset(map->push_ranges, 0, sizeof(map->push_ranges));
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bool has_const_ubo = false;
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unsigned push_start = UINT_MAX, push_end = 0;
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nir_foreach_function_impl(impl, nir) {
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nir_foreach_block(block, impl) {
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nir_foreach_instr(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo:
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if (brw_nir_ubo_surface_index_is_pushable(intrin->src[0]) &&
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nir_src_is_const(intrin->src[1]))
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has_const_ubo = true;
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break;
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case nir_intrinsic_load_push_constant: {
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unsigned base = nir_intrinsic_base(intrin);
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unsigned range = nir_intrinsic_range(intrin);
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push_start = MIN2(push_start, base);
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push_end = MAX2(push_end, base + range);
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break;
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}
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case nir_intrinsic_load_desc_set_address_intel:
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case nir_intrinsic_load_desc_set_dynamic_index_intel: {
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unsigned base = offsetof(struct anv_push_constants,
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desc_surface_offsets);
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push_start = MIN2(push_start, base);
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push_end = MAX2(push_end, base +
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sizeof_field(struct anv_push_constants,
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desc_surface_offsets));
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if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
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!pdevice->uses_ex_bso) {
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base = offsetof(struct anv_push_constants,
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surfaces_base_offset);
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push_start = MIN2(push_start, base);
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push_end = MAX2(push_end, base +
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sizeof_field(struct anv_push_constants,
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surfaces_base_offset));
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}
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break;
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}
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default:
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break;
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}
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}
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}
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}
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const bool has_push_intrinsic = push_start <= push_end;
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const bool push_ubo_ranges =
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has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE &&
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!brw_shader_stage_requires_bindless_resources(nir->info.stage);
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if (push_ubo_ranges && (robust_flags & BRW_ROBUSTNESS_UBO)) {
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/* We can't on-the-fly adjust our push ranges because doing so would
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* mess up the layout in the shader. When robustBufferAccess is
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* enabled, we push a mask into the shader indicating which pushed
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* registers are valid and we zero out the invalid ones at the top of
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* the shader.
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*/
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const uint32_t push_reg_mask_start =
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offsetof(struct anv_push_constants, push_reg_mask[nir->info.stage]);
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const uint32_t push_reg_mask_end = push_reg_mask_start + sizeof(uint64_t);
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push_start = MIN2(push_start, push_reg_mask_start);
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push_end = MAX2(push_end, push_reg_mask_end);
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}
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if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
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const uint32_t fs_msaa_flags_start =
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offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
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const uint32_t fs_msaa_flags_end = fs_msaa_flags_start + sizeof(uint32_t);
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push_start = MIN2(push_start, fs_msaa_flags_start);
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push_end = MAX2(push_end, fs_msaa_flags_end);
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}
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if (nir->info.stage == MESA_SHADER_COMPUTE && devinfo->verx10 < 125) {
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/* For compute shaders, we always have to have the subgroup ID. The
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* back-end compiler will "helpfully" add it for us in the last push
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* constant slot. Yes, there is an off-by-one error here but that's
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* because the back-end will add it so we want to claim the number of
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* push constants one dword less than the full amount including
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* gl_SubgroupId.
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*/
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assert(push_end <= offsetof(struct anv_push_constants, cs.subgroup_id));
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push_end = offsetof(struct anv_push_constants, cs.subgroup_id);
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}
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/* Align push_start down to a 32B boundary and make it no larger than
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* push_end (no push constants is indicated by push_start = UINT_MAX).
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*/
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push_start = MIN2(push_start, push_end);
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push_start = ROUND_DOWN_TO(push_start, 32);
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/* For scalar, push data size needs to be aligned to a DWORD. */
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const unsigned alignment = 4;
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nir->num_uniforms = ALIGN(push_end - push_start, alignment);
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prog_data->nr_params = nir->num_uniforms / 4;
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prog_data->param = rzalloc_array(mem_ctx, uint32_t, prog_data->nr_params);
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struct anv_push_range push_constant_range = {
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.set = ANV_DESCRIPTOR_SET_PUSH_CONSTANTS,
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.start = push_start / 32,
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.length = DIV_ROUND_UP(push_end - push_start, 32),
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};
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if (has_push_intrinsic) {
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nir_foreach_function_impl(impl, nir) {
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nir_builder build = nir_builder_create(impl);
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nir_builder *b = &build;
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_push_constant: {
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/* With bindless shaders we load uniforms with SEND
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* messages. All the push constants are located after the
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* RT_DISPATCH_GLOBALS. We just need to add the offset to
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* the address right after RT_DISPATCH_GLOBALS (see
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* brw_nir_lower_rt_intrinsics.c).
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*/
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unsigned base_offset =
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brw_shader_stage_requires_bindless_resources(nir->info.stage) ? 0 : push_start;
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intrin->intrinsic = nir_intrinsic_load_uniform;
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nir_intrinsic_set_base(intrin,
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nir_intrinsic_base(intrin) -
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base_offset);
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break;
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}
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case nir_intrinsic_load_desc_set_address_intel: {
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assert(brw_shader_stage_requires_bindless_resources(nir->info.stage));
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b->cursor = nir_before_instr(&intrin->instr);
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nir_def *desc_offset = nir_load_uniform(b, 1, 32,
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nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
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.base = offsetof(struct anv_push_constants,
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desc_surface_offsets),
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.range = sizeof_field(struct anv_push_constants,
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desc_surface_offsets),
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.dest_type = nir_type_uint32);
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desc_offset = nir_iand_imm(b, desc_offset, ANV_DESCRIPTOR_SET_OFFSET_MASK);
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if (desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER &&
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!pdevice->uses_ex_bso) {
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nir_def *bindless_base_offset = nir_load_uniform(
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b, 1, 32,
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nir_imm_int(b, 0),
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.base = offsetof(struct anv_push_constants,
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surfaces_base_offset),
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.range = sizeof_field(struct anv_push_constants,
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surfaces_base_offset),
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.dest_type = nir_type_uint32);
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desc_offset = nir_iadd(b, bindless_base_offset, desc_offset);
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}
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nir_def *desc_addr =
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nir_pack_64_2x32_split(
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b, desc_offset,
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nir_load_reloc_const_intel(
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b,
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desc_type == ANV_PIPELINE_DESCRIPTOR_SET_LAYOUT_TYPE_BUFFER ?
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BRW_SHADER_RELOC_DESCRIPTORS_BUFFER_ADDR_HIGH :
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BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH));
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nir_def_rewrite_uses(&intrin->def, desc_addr);
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break;
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}
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case nir_intrinsic_load_desc_set_dynamic_index_intel: {
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b->cursor = nir_before_instr(&intrin->instr);
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nir_def *pc_load = nir_load_uniform(b, 1, 32,
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nir_imul_imm(b, intrin->src[0].ssa, sizeof(uint32_t)),
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.base = offsetof(struct anv_push_constants,
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desc_surface_offsets),
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.range = sizeof_field(struct anv_push_constants,
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desc_surface_offsets),
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.dest_type = nir_type_uint32);
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pc_load = nir_iand_imm(
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b, pc_load, ANV_DESCRIPTOR_SET_DYNAMIC_INDEX_MASK);
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nir_def_rewrite_uses(&intrin->def, pc_load);
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break;
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}
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default:
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break;
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}
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}
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}
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}
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}
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if (push_ubo_ranges) {
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brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
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const unsigned max_push_regs = 64;
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unsigned total_push_regs = push_constant_range.length;
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for (unsigned i = 0; i < 4; i++) {
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if (total_push_regs + prog_data->ubo_ranges[i].length > max_push_regs)
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prog_data->ubo_ranges[i].length = max_push_regs - total_push_regs;
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total_push_regs += prog_data->ubo_ranges[i].length;
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}
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assert(total_push_regs <= max_push_regs);
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int n = 0;
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if (push_constant_range.length > 0)
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map->push_ranges[n++] = push_constant_range;
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if (robust_flags & BRW_ROBUSTNESS_UBO) {
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const uint32_t push_reg_mask_offset =
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offsetof(struct anv_push_constants, push_reg_mask[nir->info.stage]);
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assert(push_reg_mask_offset >= push_start);
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prog_data->push_reg_mask_param =
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(push_reg_mask_offset - push_start) / 4;
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}
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unsigned range_start_reg = push_constant_range.length;
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for (int i = 0; i < 4; i++) {
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struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
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if (ubo_range->length == 0)
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continue;
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if (n >= 4) {
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memset(ubo_range, 0, sizeof(*ubo_range));
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continue;
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}
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assert(ubo_range->block < push_map->block_count);
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const struct anv_pipeline_binding *binding =
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&push_map->block_to_descriptor[ubo_range->block];
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map->push_ranges[n++] = (struct anv_push_range) {
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.set = binding->set,
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.index = binding->index,
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.dynamic_offset_index = binding->dynamic_offset_index,
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.start = ubo_range->start,
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.length = ubo_range->length,
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};
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/* We only bother to shader-zero pushed client UBOs */
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if (binding->set < MAX_SETS &&
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(robust_flags & BRW_ROBUSTNESS_UBO)) {
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prog_data->zero_push_reg |= BITFIELD64_RANGE(range_start_reg,
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ubo_range->length);
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}
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range_start_reg += ubo_range->length;
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}
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} else {
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/* For Ivy Bridge, the push constants packets have a different
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* rule that would require us to iterate in the other direction
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* and possibly mess around with dynamic state base address.
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* Don't bother; just emit regular push constants at n = 0.
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*
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* In the compute case, we don't have multiple push ranges so it's
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* better to just provide one in push_ranges[0].
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*/
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map->push_ranges[0] = push_constant_range;
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}
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if (nir->info.stage == MESA_SHADER_FRAGMENT && fragment_dynamic) {
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struct brw_wm_prog_data *wm_prog_data =
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container_of(prog_data, struct brw_wm_prog_data, base);
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const uint32_t fs_msaa_flags_offset =
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offsetof(struct anv_push_constants, gfx.fs_msaa_flags);
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assert(fs_msaa_flags_offset >= push_start);
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wm_prog_data->msaa_flags_param =
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(fs_msaa_flags_offset - push_start) / 4;
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}
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#if 0
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fprintf(stderr, "stage=%s push ranges:\n", gl_shader_stage_name(nir->info.stage));
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for (unsigned i = 0; i < ARRAY_SIZE(map->push_ranges); i++)
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fprintf(stderr, " range%i: %03u-%03u set=%u index=%u\n", i,
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map->push_ranges[i].start,
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map->push_ranges[i].length,
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map->push_ranges[i].set,
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map->push_ranges[i].index);
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#endif
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/* Now that we're done computing the push constant portion of the
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* bind map, hash it. This lets us quickly determine if the actual
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* mapping has changed and not just a no-op pipeline change.
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*/
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_mesa_sha1_compute(map->push_ranges,
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sizeof(map->push_ranges),
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map->push_sha1);
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}
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void
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anv_nir_validate_push_layout(struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map)
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{
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#ifndef NDEBUG
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unsigned prog_data_push_size = DIV_ROUND_UP(prog_data->nr_params, 8);
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for (unsigned i = 0; i < 4; i++)
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prog_data_push_size += prog_data->ubo_ranges[i].length;
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unsigned bind_map_push_size = 0;
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for (unsigned i = 0; i < 4; i++)
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bind_map_push_size += map->push_ranges[i].length;
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/* We could go through everything again but it should be enough to assert
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* that they push the same number of registers. This should alert us if
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* the back-end compiler decides to re-arrange stuff or shrink a range.
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*/
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assert(prog_data_push_size == bind_map_push_size);
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#endif
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}
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