Samuel Pitoiset 53dc5f774d radv: only emit the per-vertex VRS state if the pipeline forced it ... If the primitive shading rate is not written by the last VGT stage (like if no FS), it's useless to emit the VRS state. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14907>		2022-02-09 17:40:37 +01:00
..
addrlib	amd/addrlib: Use get_supported_arguments to get compiler args.	2021-11-24 07:03:54 +00:00
ci	ci: Bump VK-GL-CTS to 1.3.1.0.	2022-02-08 22:16:36 +00:00
common	ac/nir: use shorter builder names	2022-01-21 13:45:33 +00:00
compiler	radv: rewrite RADV_FORCE_VRS directly in NIR	2022-02-09 17:40:34 +01:00
drm-shim	r300/r600: Add drm-shim support.	2022-02-02 00:59:08 +00:00
llvm	radv,aco,ac/llvm: implement fmulz and ffmaz	2022-01-20 22:54:42 +00:00
registers	amd/registers: work around an assertion in parse_kernel_headers.py	2022-01-05 12:46:30 +00:00
vulkan	radv: only emit the per-vertex VRS state if the pipeline forced it	2022-02-09 17:40:37 +01:00
.clang-format	radv: Add clang-format for AMD code.	2021-04-10 03:31:32 +02:00
meson.build	r300/r600: Add drm-shim support.	2022-02-02 00:59:08 +00:00