Sagar Ghuge 536ef0b546 anv: Exclude non-standard block shapes on Xe2+ ... Xe2 and Xe3 are using the same TILE64 format. So reject the non-standard MSAA shapes on Xe3 as well. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33565>		2025-02-20 02:18:19 +00:00
..
blorp	blorp: emit 3DSTATE_VF	2025-02-13 14:36:15 +00:00
ci	anv/ci/adl: update fail expectation for video	2025-02-18 18:34:51 +00:00
common	intel/common: fix mi_builder_test issue	2025-02-04 12:57:19 +00:00
compiler	brw: don't always set cond_modifier on parsed assembly instructions	2025-02-18 23:44:32 +00:00
decoder	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00
dev	intel/dev: Call intel_device_info_update_after_hwconfig() from common code	2025-02-17 20:52:31 +00:00
ds	anv: add source hashes for BVH building shaders	2025-02-07 07:27:54 +00:00
executor	intel: Initialize upper 32bits of drm_xe_sync.handle	2025-02-02 21:34:45 -08:00
genxml	intel: Fix typos	2025-02-15 17:43:44 +00:00
isl	isl: use workaround framework for Wa_1207137018	2025-01-29 12:10:13 +00:00
nullhw-layer	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
perf	intel/perf: add new perf consts to support more metrics	2025-01-16 00:01:56 +00:00
shaders	intel: output a depfile with mesa_clc	2025-02-04 00:10:01 +00:00
tools	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00
vulkan	anv: Exclude non-standard block shapes on Xe2+	2025-02-20 02:18:19 +00:00
vulkan_hasvk	intel: switch to nir_metadata_divergence	2025-02-13 10:08:43 +00:00
meson.build	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00