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Generated by: sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.c sed -i -e 's/brw_device_info/gen_device_info/g' src/intel/**/*.h sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.c sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.cpp sed -i -e 's/brw_device_info/gen_device_info/g' **/i965/*.h Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
306 lines
10 KiB
C
306 lines
10 KiB
C
/*
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* Copyright 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "isl_priv.h"
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#include "brw_compiler.h"
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bool
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isl_is_storage_image_format(enum isl_format format)
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{
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/* XXX: Maybe we should put this in the CSV? */
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switch (format) {
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case ISL_FORMAT_R32G32B32A32_UINT:
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case ISL_FORMAT_R32G32B32A32_SINT:
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case ISL_FORMAT_R32G32B32A32_FLOAT:
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case ISL_FORMAT_R32_UINT:
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case ISL_FORMAT_R32_SINT:
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case ISL_FORMAT_R32_FLOAT:
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case ISL_FORMAT_R16G16B16A16_UINT:
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case ISL_FORMAT_R16G16B16A16_SINT:
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case ISL_FORMAT_R16G16B16A16_FLOAT:
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case ISL_FORMAT_R32G32_UINT:
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case ISL_FORMAT_R32G32_SINT:
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case ISL_FORMAT_R32G32_FLOAT:
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case ISL_FORMAT_R8G8B8A8_UINT:
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case ISL_FORMAT_R8G8B8A8_SINT:
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case ISL_FORMAT_R16G16_UINT:
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case ISL_FORMAT_R16G16_SINT:
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case ISL_FORMAT_R16G16_FLOAT:
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case ISL_FORMAT_R8G8_UINT:
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case ISL_FORMAT_R8G8_SINT:
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case ISL_FORMAT_R16_UINT:
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case ISL_FORMAT_R16_FLOAT:
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case ISL_FORMAT_R16_SINT:
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case ISL_FORMAT_R8_UINT:
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case ISL_FORMAT_R8_SINT:
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case ISL_FORMAT_R10G10B10A2_UINT:
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case ISL_FORMAT_R10G10B10A2_UNORM:
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case ISL_FORMAT_R11G11B10_FLOAT:
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case ISL_FORMAT_R16G16B16A16_UNORM:
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case ISL_FORMAT_R16G16B16A16_SNORM:
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case ISL_FORMAT_R8G8B8A8_UNORM:
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case ISL_FORMAT_R8G8B8A8_SNORM:
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case ISL_FORMAT_R16G16_UNORM:
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case ISL_FORMAT_R16G16_SNORM:
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case ISL_FORMAT_R8G8_UNORM:
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case ISL_FORMAT_R8G8_SNORM:
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case ISL_FORMAT_R16_UNORM:
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case ISL_FORMAT_R16_SNORM:
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case ISL_FORMAT_R8_UNORM:
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case ISL_FORMAT_R8_SNORM:
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return true;
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default:
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return false;
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}
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}
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enum isl_format
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isl_lower_storage_image_format(const struct gen_device_info *devinfo,
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enum isl_format format)
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{
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switch (format) {
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/* These are never lowered. Up to BDW we'll have to fall back to untyped
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* surface access for 128bpp formats.
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*/
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case ISL_FORMAT_R32G32B32A32_UINT:
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case ISL_FORMAT_R32G32B32A32_SINT:
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case ISL_FORMAT_R32G32B32A32_FLOAT:
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case ISL_FORMAT_R32_UINT:
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case ISL_FORMAT_R32_SINT:
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case ISL_FORMAT_R32_FLOAT:
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return format;
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/* From HSW to BDW the only 64bpp format supported for typed access is
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* RGBA_UINT16. IVB falls back to untyped.
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*/
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case ISL_FORMAT_R16G16B16A16_UINT:
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case ISL_FORMAT_R16G16B16A16_SINT:
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case ISL_FORMAT_R16G16B16A16_FLOAT:
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case ISL_FORMAT_R32G32_UINT:
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case ISL_FORMAT_R32G32_SINT:
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case ISL_FORMAT_R32G32_FLOAT:
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return (devinfo->gen >= 9 ? format :
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devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R16G16B16A16_UINT :
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ISL_FORMAT_R32G32_UINT);
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/* Up to BDW no SINT or FLOAT formats of less than 32 bits per component
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* are supported. IVB doesn't support formats with more than one component
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* for typed access. For 8 and 16 bpp formats IVB relies on the
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* undocumented behavior that typed reads from R_UINT8 and R_UINT16
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* surfaces actually do a 32-bit misaligned read. The alternative would be
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* to use two surface state entries with different formats for each image,
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* one for reading (using R_UINT32) and another one for writing (using
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* R_UINT8 or R_UINT16), but that would complicate the shaders we generate
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* even more.
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*/
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case ISL_FORMAT_R8G8B8A8_UINT:
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case ISL_FORMAT_R8G8B8A8_SINT:
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return (devinfo->gen >= 9 ? format :
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devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
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case ISL_FORMAT_R16G16_UINT:
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case ISL_FORMAT_R16G16_SINT:
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case ISL_FORMAT_R16G16_FLOAT:
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return (devinfo->gen >= 9 ? format :
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devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
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case ISL_FORMAT_R8G8_UINT:
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case ISL_FORMAT_R8G8_SINT:
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return (devinfo->gen >= 9 ? format :
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devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
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case ISL_FORMAT_R16_UINT:
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case ISL_FORMAT_R16_FLOAT:
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case ISL_FORMAT_R16_SINT:
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return (devinfo->gen >= 9 ? format : ISL_FORMAT_R16_UINT);
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case ISL_FORMAT_R8_UINT:
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case ISL_FORMAT_R8_SINT:
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return (devinfo->gen >= 9 ? format : ISL_FORMAT_R8_UINT);
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/* Neither the 2/10/10/10 nor the 11/11/10 packed formats are supported
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* by the hardware.
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*/
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case ISL_FORMAT_R10G10B10A2_UINT:
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case ISL_FORMAT_R10G10B10A2_UNORM:
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case ISL_FORMAT_R11G11B10_FLOAT:
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return ISL_FORMAT_R32_UINT;
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/* No normalized fixed-point formats are supported by the hardware. */
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case ISL_FORMAT_R16G16B16A16_UNORM:
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case ISL_FORMAT_R16G16B16A16_SNORM:
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return (devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R16G16B16A16_UINT :
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ISL_FORMAT_R32G32_UINT);
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case ISL_FORMAT_R8G8B8A8_UNORM:
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case ISL_FORMAT_R8G8B8A8_SNORM:
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return (devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R8G8B8A8_UINT : ISL_FORMAT_R32_UINT);
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case ISL_FORMAT_R16G16_UNORM:
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case ISL_FORMAT_R16G16_SNORM:
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return (devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R16G16_UINT : ISL_FORMAT_R32_UINT);
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case ISL_FORMAT_R8G8_UNORM:
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case ISL_FORMAT_R8G8_SNORM:
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return (devinfo->gen >= 8 || devinfo->is_haswell ?
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ISL_FORMAT_R8G8_UINT : ISL_FORMAT_R16_UINT);
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case ISL_FORMAT_R16_UNORM:
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case ISL_FORMAT_R16_SNORM:
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return ISL_FORMAT_R16_UINT;
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case ISL_FORMAT_R8_UNORM:
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case ISL_FORMAT_R8_SNORM:
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return ISL_FORMAT_R8_UINT;
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default:
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assert(!"Unknown image format");
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return ISL_FORMAT_UNSUPPORTED;
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}
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}
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bool
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isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
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enum isl_format fmt)
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{
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if (devinfo->gen >= 9) {
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return true;
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} else if (devinfo->gen >= 8 || devinfo->is_haswell) {
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return isl_format_get_layout(fmt)->bpb <= 64;
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} else {
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return isl_format_get_layout(fmt)->bpb <= 32;
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}
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}
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static const struct brw_image_param image_param_defaults = {
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/* Set the swizzling shifts to all-ones to effectively disable
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* swizzling -- See emit_address_calculation() in
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* brw_fs_surface_builder.cpp for a more detailed explanation of
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* these parameters.
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*/
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.swizzling = { 0xff, 0xff },
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};
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void
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isl_surf_fill_image_param(const struct isl_device *dev,
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struct brw_image_param *param,
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const struct isl_surf *surf,
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const struct isl_view *view)
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{
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*param = image_param_defaults;
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param->size[0] = isl_minify(surf->logical_level0_px.w, view->base_level);
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param->size[1] = isl_minify(surf->logical_level0_px.h, view->base_level);
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if (surf->dim == ISL_SURF_DIM_3D) {
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param->size[2] = isl_minify(surf->logical_level0_px.d, view->base_level);
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} else {
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param->size[2] = surf->logical_level0_px.array_len -
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view->base_array_layer;
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}
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isl_surf_get_image_offset_el(surf, view->base_level, view->base_array_layer,
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0, ¶m->offset[0], ¶m->offset[1]);
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const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
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param->stride[0] = cpp;
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param->stride[1] = surf->row_pitch / cpp;
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const struct isl_extent3d image_align_sa =
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isl_surf_get_image_alignment_sa(surf);
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if (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) {
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param->stride[2] = isl_align_npot(param->size[0], image_align_sa.w);
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param->stride[3] = isl_align_npot(param->size[1], image_align_sa.h);
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} else {
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param->stride[2] = 0;
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param->stride[3] = isl_surf_get_array_pitch_el_rows(surf);
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}
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switch (surf->tiling) {
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case ISL_TILING_LINEAR:
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/* image_param_defaults is good enough */
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break;
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case ISL_TILING_X:
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/* An X tile is a rectangular block of 512x8 bytes. */
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param->tiling[0] = isl_log2u(512 / cpp);
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param->tiling[1] = isl_log2u(8);
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if (dev->has_bit6_swizzling) {
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/* Right shifts required to swizzle bits 9 and 10 of the memory
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* address with bit 6.
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*/
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param->swizzling[0] = 3;
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param->swizzling[1] = 4;
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}
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break;
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case ISL_TILING_Y0:
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/* The layout of a Y-tiled surface in memory isn't really fundamentally
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* different to the layout of an X-tiled surface, we simply pretend that
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* the surface is broken up in a number of smaller 16Bx32 tiles, each
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* one arranged in X-major order just like is the case for X-tiling.
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*/
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param->tiling[0] = isl_log2u(16 / cpp);
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param->tiling[1] = isl_log2u(32);
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if (dev->has_bit6_swizzling) {
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/* Right shift required to swizzle bit 9 of the memory address with
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* bit 6.
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*/
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param->swizzling[0] = 3;
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param->swizzling[1] = 0xff;
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}
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break;
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default:
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assert(!"Unhandled storage image tiling");
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}
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/* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
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* address calculation algorithm (emit_address_calculation() in
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* brw_fs_surface_builder.cpp) handles this as a sort of tiling with
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* modulus equal to the LOD.
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*/
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param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
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view->base_level : 0);
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}
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void
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isl_buffer_fill_image_param(const struct isl_device *dev,
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struct brw_image_param *param,
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enum isl_format format,
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uint64_t size)
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{
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*param = image_param_defaults;
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param->stride[0] = isl_format_layouts[format].bpb / 8;
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param->size[0] = size / param->stride[0];
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}
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