mesa/src/intel
Caio Oliveira 390317a99e brw: Fix size in assembler when compacting
Calculation was wrongly walking uncompacted instructions, even if we had
some compacted in the middle, generating invalid size.  Since we are
here just drop the instruction count, since in practice the caller will
have to walk the instruction stream anyway.

Fixes: 6267585778 ("intel/brw: Also return the size of the assembled shader")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33532>
(cherry picked from commit dd1ca1588d)
2025-03-04 20:24:05 +01:00
..
blorp intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
ci iris: fix handling of GL_*_VERTEX_CONVENTION 2025-02-28 22:17:35 +01:00
common intel/common/xe2+: Allow SIMD32 PS for all multisample cases. 2025-01-29 23:39:32 +00:00
compiler brw: Fix size in assembler when compacting 2025-03-04 20:24:05 +01:00
decoder intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
dev intel/brw: Use SHADER_OPCODE_SEND_GATHER in Xe3 2025-01-30 04:43:58 +00:00
ds intel : Expose Shader hashes for utrace and Perfetto 2025-01-10 17:38:16 +00:00
executor intel/executor: Fix typo when copying result into Lua table 2025-01-29 09:57:23 +00:00
genxml anv/xe3+: Set RegistersPerThread for bindless shader dispatch. 2025-01-29 23:39:32 +00:00
isl isl: use workaround framework for Wa_1207137018 2025-01-29 12:10:13 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/perf: add new perf consts to support more metrics 2025-01-16 00:01:56 +00:00
shaders clc,libagx: automatically set lang version 2025-01-28 23:01:32 +00:00
tools intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
vulkan anv: Do not support the tiling of DRM modifier if DECODE_DST 2025-03-03 17:25:22 +01:00
vulkan_hasvk hasvk: disable logic op for float/srgb formats 2025-01-29 08:02:21 +00:00
meson.build intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00