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f5981e8c0b
To keep track which output is used for what purpose. Note that this commit just adds the capability to track this separately in ac/nir. The drivers will need to be updated in the future to take advantage of this. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32640>
341 lines
11 KiB
C
341 lines
11 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_NIR_H
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#define AC_NIR_H
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#include "ac_hw_stage.h"
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#include "ac_shader_args.h"
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#include "ac_shader_util.h"
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#include "nir.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Reserve this size at the beginning of LDS for the tf0/1 shader message group vote. */
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#define AC_HS_MSG_VOTE_LDS_BYTES 16
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enum
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{
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/* SPI_PS_INPUT_CNTL_i.OFFSET[0:4] */
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AC_EXP_PARAM_OFFSET_0 = 0,
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AC_EXP_PARAM_OFFSET_31 = 31,
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/* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL[0:1] */
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AC_EXP_PARAM_DEFAULT_VAL_0000 = 64,
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AC_EXP_PARAM_DEFAULT_VAL_0001,
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AC_EXP_PARAM_DEFAULT_VAL_1110,
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AC_EXP_PARAM_DEFAULT_VAL_1111,
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AC_EXP_PARAM_UNDEFINED = 255, /* deprecated, use AC_EXP_PARAM_DEFAULT_VAL_0000 instead */
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};
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enum {
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AC_EXP_FLAG_COMPRESSED = (1 << 0),
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AC_EXP_FLAG_DONE = (1 << 1),
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AC_EXP_FLAG_VALID_MASK = (1 << 2),
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};
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/* Maps I/O semantics to the actual location used by the lowering pass. */
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typedef unsigned (*ac_nir_map_io_driver_location)(unsigned semantic);
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/* Forward declaration of nir_builder so we don't have to include nir_builder.h here */
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struct nir_builder;
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typedef struct nir_builder nir_builder;
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/* Executed by ac_nir_cull when the current primitive is accepted. */
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typedef void (*ac_nir_cull_accepted)(nir_builder *b, void *state);
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nir_def *
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ac_nir_load_arg_at_offset(nir_builder *b, const struct ac_shader_args *ac_args,
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struct ac_arg arg, unsigned relative_index);
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static inline nir_def *
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ac_nir_load_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg)
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{
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return ac_nir_load_arg_at_offset(b, ac_args, arg, 0);
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}
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void ac_nir_store_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg,
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nir_def *val);
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nir_def *
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ac_nir_unpack_arg(nir_builder *b, const struct ac_shader_args *ac_args, struct ac_arg arg,
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unsigned rshift, unsigned bitwidth);
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bool ac_nir_lower_sin_cos(nir_shader *shader);
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bool ac_nir_lower_intrinsics_to_args(nir_shader *shader, const enum amd_gfx_level gfx_level,
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const enum ac_hw_stage hw_stage,
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const struct ac_shader_args *ac_args);
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bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
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uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]);
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void
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ac_nir_lower_ls_outputs_to_mem(nir_shader *ls,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool tcs_in_out_eq,
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uint64_t tcs_inputs_via_temp,
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uint64_t tcs_inputs_via_lds);
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void
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ac_nir_lower_hs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool tcs_in_out_eq,
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uint64_t tcs_inputs_via_temp,
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uint64_t tcs_inputs_via_lds);
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void
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ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, const nir_tcs_info *info,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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uint64_t tes_inputs_read,
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uint32_t tes_patch_inputs_read,
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unsigned wave_size);
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void
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ac_nir_lower_tes_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map);
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void
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ac_nir_compute_tess_wg_info(const struct radeon_info *info, const struct shader_info *tcs_info,
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unsigned wave_size, bool tess_uses_primid, bool all_invocations_define_tess_levels,
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unsigned num_tcs_input_cp, unsigned lds_input_vertex_size,
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unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs,
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unsigned *num_patches_per_wg, unsigned *hw_lds_size);
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void
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ac_nir_lower_es_outputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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unsigned esgs_itemsize,
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uint64_t gs_inputs_read);
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void
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ac_nir_lower_gs_inputs_to_mem(nir_shader *shader,
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ac_nir_map_io_driver_location map,
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enum amd_gfx_level gfx_level,
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bool triangle_strip_adjacency_fix);
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bool
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ac_nir_lower_indirect_derefs(nir_shader *shader,
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enum amd_gfx_level gfx_level);
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typedef struct {
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enum radeon_family family;
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enum amd_gfx_level gfx_level;
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unsigned max_workgroup_size;
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unsigned wave_size;
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uint8_t clip_cull_dist_mask;
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const uint8_t *vs_output_param_offset; /* GFX11+ */
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bool has_param_exports;
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bool can_cull;
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bool disable_streamout;
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bool has_gen_prim_query;
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bool has_xfb_prim_query;
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bool use_gfx12_xfb_intrinsic;
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bool has_gs_invocations_query;
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bool has_gs_primitives_query;
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bool kill_pointsize;
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bool kill_layer;
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bool force_vrs;
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bool compact_primitives;
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/* VS */
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unsigned num_vertices_per_primitive;
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bool early_prim_export;
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bool passthrough;
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bool use_edgeflags;
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bool export_primitive_id;
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bool export_primitive_id_per_prim;
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uint32_t instance_rate_inputs;
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uint32_t user_clip_plane_enable_mask;
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/* GS */
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unsigned gs_out_vtx_bytes;
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} ac_nir_lower_ngg_options;
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void
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ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *options);
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void
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ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options);
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void
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ac_nir_lower_ngg_ms(nir_shader *shader,
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enum amd_gfx_level gfx_level,
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uint32_t clipdist_enable_mask,
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const uint8_t *vs_output_param_offset,
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bool has_param_exports,
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bool *out_needs_scratch_ring,
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unsigned wave_size,
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unsigned workgroup_size,
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bool multiview,
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bool has_query,
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bool fast_launch_2);
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void
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ac_nir_lower_task_outputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries,
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bool has_query);
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void
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ac_nir_lower_mesh_inputs_to_mem(nir_shader *shader,
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unsigned task_payload_entry_bytes,
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unsigned task_num_entries);
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bool
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ac_nir_lower_global_access(nir_shader *shader);
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bool ac_nir_lower_resinfo(nir_shader *nir, enum amd_gfx_level gfx_level);
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bool ac_nir_lower_image_opcodes(nir_shader *nir);
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typedef struct ac_nir_gs_output_info {
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const uint8_t *streams;
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const uint8_t *streams_16bit_lo;
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const uint8_t *streams_16bit_hi;
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const uint8_t *varying_mask;
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const uint8_t *varying_mask_16bit_lo;
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const uint8_t *varying_mask_16bit_hi;
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const uint8_t *sysval_mask;
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/* type for each 16bit slot component */
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nir_alu_type (*types_16bit_lo)[4];
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nir_alu_type (*types_16bit_hi)[4];
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} ac_nir_gs_output_info;
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nir_shader *
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ac_nir_create_gs_copy_shader(const nir_shader *gs_nir,
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enum amd_gfx_level gfx_level,
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uint32_t clip_cull_mask,
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const uint8_t *param_offsets,
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bool has_param_exports,
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bool disable_streamout,
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bool kill_pointsize,
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bool kill_layer,
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bool force_vrs,
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ac_nir_gs_output_info *output_info);
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void
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ac_nir_lower_legacy_vs(nir_shader *nir,
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enum amd_gfx_level gfx_level,
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uint32_t clip_cull_mask,
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const uint8_t *param_offsets,
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bool has_param_exports,
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bool export_primitive_id,
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bool disable_streamout,
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bool kill_pointsize,
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bool kill_layer,
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bool force_vrs);
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bool
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ac_nir_gs_shader_query(nir_builder *b,
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bool has_gen_prim_query,
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bool has_gs_invocations_query,
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bool has_gs_primitives_query,
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unsigned num_vertices_per_primitive,
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unsigned wave_size,
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nir_def *vertex_count[4],
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nir_def *primitive_count[4]);
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void
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ac_nir_lower_legacy_gs(nir_shader *nir,
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bool has_gen_prim_query,
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bool has_pipeline_stats_query,
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ac_nir_gs_output_info *output_info);
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typedef struct {
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enum radeon_family family;
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enum amd_gfx_level gfx_level;
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bool use_aco;
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bool uses_discard;
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bool alpha_to_coverage_via_mrtz;
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bool dual_src_blend_swizzle;
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unsigned spi_shader_col_format;
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unsigned color_is_int8;
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unsigned color_is_int10;
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bool bc_optimize_for_persp;
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bool bc_optimize_for_linear;
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bool force_persp_sample_interp;
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bool force_linear_sample_interp;
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bool force_persp_center_interp;
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bool force_linear_center_interp;
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unsigned ps_iter_samples;
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/* OpenGL only */
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bool clamp_color;
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bool alpha_to_one;
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enum compare_func alpha_func;
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unsigned broadcast_last_cbuf;
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bool kill_z;
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bool kill_stencil;
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bool kill_samplemask;
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/* Vulkan only */
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unsigned enable_mrt_output_nan_fixup;
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bool no_color_export;
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bool no_depth_export;
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} ac_nir_lower_ps_options;
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void
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ac_nir_lower_ps(nir_shader *nir, const ac_nir_lower_ps_options *options);
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typedef struct {
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enum amd_gfx_level gfx_level;
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/* If true, round the layer component of the coordinates source to the nearest
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* integer for all array ops. This is always done for cube array ops.
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*/
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bool lower_array_layer_round_even;
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/* Fix derivatives of constants and FS inputs in control flow.
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*
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* Ignores interpolateAtSample()/interpolateAtOffset(), dynamically indexed input loads,
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* pervertexEXT input loads, textureGather() with implicit LOD and 16-bit derivatives and
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* texture samples with nir_tex_src_min_lod.
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*
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* The layer must also be a constant or FS input.
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*/
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bool fix_derivs_in_divergent_cf;
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unsigned max_wqm_vgprs;
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} ac_nir_lower_tex_options;
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bool
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ac_nir_lower_tex(nir_shader *nir, const ac_nir_lower_tex_options *options);
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void
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ac_nir_store_debug_log_amd(nir_builder *b, nir_def *uvec4);
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bool
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ac_nir_opt_pack_half(nir_shader *shader, enum amd_gfx_level gfx_level);
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unsigned
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ac_nir_varying_expression_max_cost(nir_shader *producer, nir_shader *consumer);
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bool
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ac_nir_opt_shared_append(nir_shader *shader);
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bool
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ac_nir_flag_smem_for_loads(nir_shader *shader, enum amd_gfx_level gfx_level, bool use_llvm, bool after_lowering);
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bool
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ac_nir_lower_mem_access_bit_sizes(nir_shader *shader, enum amd_gfx_level gfx_level, bool use_llvm);
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#ifdef __cplusplus
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}
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#endif
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#endif /* AC_NIR_H */
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