Ian Romanick 4a238f461d brw: Do cmod prop again after brw_lower_subgroup_ops ... shader-db: All Intel platforms had similar results. (Lunar Lake shown) total instructions in shared programs: 17114300 -> 17114294 (<.01%) instructions in affected programs: 3617 -> 3611 (-0.17%) helped: 6 / HURT: 0 total cycles in shared programs: 886397556 -> 886397454 (<.01%) cycles in affected programs: 511400 -> 511298 (-0.02%) helped: 6 / HURT: 0 fossil-db: Lunar Lake Totals: Instrs: 233683694 -> 233676039 (-0.00%); split: -0.00%, +0.00% Cycle count: 32602038466 -> 32594097814 (-0.02%); split: -0.03%, +0.01% Spill count: 540908 -> 540704 (-0.04%) Fill count: 700935 -> 700258 (-0.10%) Totals from 2200 (0.28% of 789264) affected shaders: Instrs: 2062360 -> 2054705 (-0.37%); split: -0.37%, +0.00% Cycle count: 2506073282 -> 2498132630 (-0.32%); split: -0.41%, +0.09% Spill count: 14423 -> 14219 (-1.41%) Fill count: 34219 -> 33542 (-1.98%) Meteor Lake and DG2 had similar results. (Meteor Lake shown) Totals: Instrs: 263545171 -> 263543341 (-0.00%); split: -0.00%, +0.00% Cycle count: 26480835985 -> 26484748317 (+0.01%); split: -0.01%, +0.03% Spill count: 554335 -> 554338 (+0.00%) Fill count: 645486 -> 645498 (+0.00%) Totals from 610 (0.07% of 903944) affected shaders: Instrs: 1139871 -> 1138041 (-0.16%); split: -0.17%, +0.01% Cycle count: 2274612327 -> 2278524659 (+0.17%); split: -0.15%, +0.33% Spill count: 15153 -> 15156 (+0.02%) Fill count: 36831 -> 36843 (+0.03%) Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown) Totals: Instrs: 268713723 -> 268712817 (-0.00%); split: -0.00%, +0.00% Cycle count: 24653238085 -> 24652269669 (-0.00%); split: -0.00%, +0.00% Fill count: 671369 -> 671361 (-0.00%) Totals from 666 (0.07% of 899711) affected shaders: Instrs: 924423 -> 923517 (-0.10%); split: -0.11%, +0.01% Cycle count: 840380565 -> 839412149 (-0.12%); split: -0.13%, +0.02% Fill count: 13006 -> 12998 (-0.06%) Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35444>		2025-08-28 22:08:20 +00:00
..
blorp	isl/blorp: handle failing 96bpp linear blit case	2025-08-13 16:09:12 +00:00
ci	ci/piglit: automatically use LAVA proxy	2025-08-25 14:52:38 +00:00
common	intel/gem: Add an intel_gem_supports_dma_buf_sync_file() helper	2025-08-16 00:04:46 -04:00
compiler	brw: Do cmod prop again after brw_lower_subgroup_ops	2025-08-28 22:08:20 +00:00
decoder	intel/genxml: Remove support for start/end atttributes	2025-07-23 16:02:14 +00:00
dev	intel/dev: provide a helper to detect bmg g31 device	2025-08-26 19:35:33 +00:00
ds	perfetto: allow specifying clock domain for cpu timestamps	2025-08-19 09:50:36 +00:00
executor	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
genxml	intel/genxml: update CACHE_MODE_0 register for gfx200	2025-08-26 19:35:33 +00:00
isl	isl/blorp: handle failing 96bpp linear blit case	2025-08-13 16:09:12 +00:00
nullhw-layer	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
perf	intel: fork exec_node/list -> brw_exec_node/list as a private Intel utility	2025-07-31 20:23:02 +00:00
shaders	intel: use common CL args	2025-03-06 00:43:59 +00:00
tools	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
vulkan	anv: move input coverage mask setup to runtime flush	2025-08-28 19:08:33 +00:00
vulkan_hasvk	hasvk: Remove special CROS_GRALLOC path from format logic	2025-08-22 23:40:32 +00:00
meson.build	intel: Add meson option -Dintel-elk	2025-01-30 00:45:59 +00:00