Rohan Garg 49ed35c08a anv: 3D surfaces have fewer layers for higher miplevels ... Signed-off-by: Rohan Garg <rohan.garg@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>		2024-03-21 18:28:27 +00:00
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blorp	anv,blorp: implement restrictions from WA 1406738321	2024-03-21 18:28:27 +00:00
ci	ci/intel: split asus-cx9400-volteer into acer-cp514-2h-11{30,60}g7-volteer	2024-03-06 01:52:49 +00:00
common	intel/elk: Remove multi-polygon support	2024-03-07 15:53:19 +00:00
compiler	meson: Allow building intel-clc for the host if it can be run	2024-03-21 16:31:35 +00:00
decoder	intel/decoder: Add ELK support	2024-02-24 00:24:31 +00:00
dev	intel/dev: remove pci revision from shader cache key	2024-03-19 15:11:19 -07:00
ds	intel/ds: add pipe control reasons to perfetto flushes	2024-03-08 07:52:20 +00:00
genxml	anv/trtt: update GFX_TRTT_VA_RANGE for LNL	2024-03-13 01:50:35 +00:00
isl	anv/iris/blorp: use the right MOCS values for each engine	2024-03-06 20:33:12 +00:00
nullhw-layer	intel/nullhw: Fix 32bits compilation warnings	2024-02-28 23:37:43 +00:00
perf	intel: Remove unused ALIGN macro	2023-12-07 02:30:53 +00:00
shaders	intel-clc: Use correct set of nir_options when building for Gfx8	2024-02-24 00:24:32 +00:00
tools	intel/tools/error_decode: Parse HW context in Xe decoder	2024-03-21 16:59:09 +00:00
vulkan	anv: 3D surfaces have fewer layers for higher miplevels	2024-03-21 18:28:27 +00:00
vulkan_hasvk	anv/hasvk: default image_read_without_format to true	2024-03-13 19:29:04 +00:00
meson.build	intel: Only build shaders with anv and iris	2024-02-21 20:53:36 +00:00