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4c62e09505
Turing and newer Nvidia cards can work with up to 8 discard rectangles Reviewed-by: Mel Henning <mhenning@darkrefraction.com> Signed-off-by: Lorenzo Rossi <git@rossilorenzo.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33476>
99 lines
3.6 KiB
C
99 lines
3.6 KiB
C
/*
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* Copyright © 2022 Collabora, LTD
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef VK_LIMITS_H
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#define VK_LIMITS_H
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/* Maximun number of shader stages in a single graphics pipeline */
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#define MESA_VK_MAX_GRAPHICS_PIPELINE_STAGES 5
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#define MESA_VK_MAX_DESCRIPTOR_SETS 32
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/* From the Vulkan 1.3.274 spec:
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*
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* VUID-VkPipelineLayoutCreateInfo-pPushConstantRanges-00292
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*
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* "Any two elements of pPushConstantRanges must not include the same
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* stage in stageFlags"
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*
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* and
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*
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* VUID-VkPushConstantRange-stageFlags-requiredbitmask
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*
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* "stageFlags must not be 0"
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*
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* This means that the number of push constant ranges is effectively bounded
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* by the number of possible shader stages. Not the number of stages that can
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* be compiled together (a pipeline layout can be used in multiple pipelnes
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* wth different sets of shaders) but the total number of stage bits supported
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* by the implementation. Currently, those are
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*
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* - VK_SHADER_STAGE_VERTEX_BIT
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* - VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
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* - VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
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* - VK_SHADER_STAGE_GEOMETRY_BIT
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* - VK_SHADER_STAGE_FRAGMENT_BIT
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* - VK_SHADER_STAGE_COMPUTE_BIT
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* - VK_SHADER_STAGE_RAYGEN_BIT_KHR
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* - VK_SHADER_STAGE_ANY_HIT_BIT_KHR
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* - VK_SHADER_STAGE_CLOSEST_HIT_BIT_KHR
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* - VK_SHADER_STAGE_MISS_BIT_KHR
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* - VK_SHADER_STAGE_INTERSECTION_BIT_KHR
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* - VK_SHADER_STAGE_CALLABLE_BIT_KHR
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* - VK_SHADER_STAGE_TASK_BIT_EXT
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* - VK_SHADER_STAGE_MESH_BIT_EXT
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*/
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#define MESA_VK_MAX_PUSH_CONSTANT_RANGES 14
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#define MESA_VK_MAX_VERTEX_BINDINGS 32
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#define MESA_VK_MAX_VERTEX_ATTRIBUTES 32
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/* As of June 29, 2022, according to vulkan.gpuinfo.org, 99% of all reports
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* listed a max vertex stride that fits in 16 bits.
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*/
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#define MESA_VK_MAX_VERTEX_BINDING_STRIDE UINT16_MAX
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#define MESA_VK_MAX_VIEWPORTS 16
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#define MESA_VK_MAX_SCISSORS 16
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#define MESA_VK_MAX_DISCARD_RECTANGLES 8
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/* As of June 29, 2022, according to vulkan.gpuinfo.org, no reports list more
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* than 16 samples for framebufferColorSampleCounts except one layer running
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* on top of WARP on Windows.
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*/
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#define MESA_VK_MAX_SAMPLES 16
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/* As of June 29, 2022, according to vulkan.gpuinfo.org, the only GPUs
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* claiming support for maxSampleLocationGridSize greater than 1x1 is AMD
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* which supports 2x2 but only up to 8 samples.
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*/
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#define MESA_VK_MAX_SAMPLE_LOCATIONS 32
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#define MESA_VK_MAX_COLOR_ATTACHMENTS 8
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/* Since VkSubpassDescription2::viewMask is a 32-bit integer, there are a
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* maximum of 32 possible views.
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*/
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#define MESA_VK_MAX_MULTIVIEW_VIEW_COUNT 32
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#endif /* VK_LIMITS_H */
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