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mesa/src/amd
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David Rosca 8b1a889e45 radeonsi/vcn: Add support for QVBR rate control mode 
This rate control mode needs pre-encode enabled and currently is
supported for VCN3 and VCN4.
AV1 needs quality level scaled down from 255 to 51 range.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4024
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30221>
2024-07-24 20:18:49 +00:00
..
addrlib amd: add GFX v11.5.2 support 2024-07-02 12:05:23 +00:00
ci radeonsi/ci: skip timing out test 2024-07-19 21:26:16 +00:00
common radeonsi/vcn: Add support for QVBR rate control mode 2024-07-24 20:18:49 +00:00
compiler nir: add nir_intrinsic_load_per_primitive_input, split from io_semantics flag 2024-07-23 16:13:16 +00:00
drm-shim build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
llvm nir: add nir_intrinsic_load_per_primitive_input, split from io_semantics flag 2024-07-23 16:13:16 +00:00
registers amd: add gfx12 register definitions 2024-05-11 22:14:05 -04:00
vpelib amd/vpelib: support VPE IP v6.1.3 2024-07-02 12:05:23 +00:00
vulkan amd: expose nir_io_mix_convergent_flat_with_interpolated 2024-07-23 16:13:17 +00:00
meson.build build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00