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022e55557b
This new intrinsic maps to the MTBUF instruction format on AMD GPUs and represents a typed buffer load in NIR. Also add an unsigned upper bound for the new intrinsic. Code for that ported from aco_instruction_selection_setup. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16805> |
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| .. | ||
| clc | ||
| glsl | ||
| isaspec | ||
| nir | ||
| spirv | ||
| builtin_type_macros.h | ||
| glsl_types.cpp | ||
| glsl_types.h | ||
| meson.build | ||
| nir_gl_types.h | ||
| nir_types.cpp | ||
| nir_types.h | ||
| shader_enums.c | ||
| shader_enums.h | ||
| shader_info.h | ||