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1067 lines
26 KiB
C
1067 lines
26 KiB
C
/*
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* (C) Copyright IBM Corporation 2008
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* AUTHORS, COPYRIGHT HOLDERS, AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/**
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* \file
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* Real-time assembly generation interface for Cell B.E. SPEs.
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*
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* \author Ian Romanick <idr@us.ibm.com>
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* \author Brian Paul
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*/
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#include <stdio.h>
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#include "pipe/p_compiler.h"
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#include "util/u_memory.h"
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#include "rtasm_ppc_spe.h"
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#ifdef GALLIUM_CELL
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/**
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* SPE instruction types
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*
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* There are 6 primary instruction encodings used on the Cell's SPEs. Each of
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* the following unions encodes one type.
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*
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* \bug
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* If, at some point, we start generating SPE code from a little-endian host
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* these unions will not work.
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*/
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/*@{*/
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/**
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* Encode one output register with two input registers
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*/
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union spe_inst_RR {
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uint32_t bits;
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struct {
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unsigned op:11;
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unsigned rB:7;
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unsigned rA:7;
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unsigned rT:7;
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} inst;
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};
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/**
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* Encode one output register with three input registers
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*/
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union spe_inst_RRR {
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uint32_t bits;
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struct {
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unsigned op:4;
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unsigned rT:7;
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unsigned rB:7;
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unsigned rA:7;
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unsigned rC:7;
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} inst;
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};
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/**
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* Encode one output register with one input reg. and a 7-bit signed immed
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*/
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union spe_inst_RI7 {
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uint32_t bits;
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struct {
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unsigned op:11;
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unsigned i7:7;
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unsigned rA:7;
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unsigned rT:7;
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} inst;
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};
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/**
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* Encode one output register with one input reg. and an 8-bit signed immed
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*/
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union spe_inst_RI8 {
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uint32_t bits;
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struct {
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unsigned op:10;
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unsigned i8:8;
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unsigned rA:7;
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unsigned rT:7;
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} inst;
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};
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/**
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* Encode one output register with one input reg. and a 10-bit signed immed
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*/
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union spe_inst_RI10 {
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uint32_t bits;
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struct {
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unsigned op:8;
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unsigned i10:10;
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unsigned rA:7;
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unsigned rT:7;
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} inst;
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};
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/**
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* Encode one output register with a 16-bit signed immediate
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*/
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union spe_inst_RI16 {
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uint32_t bits;
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struct {
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unsigned op:9;
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unsigned i16:16;
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unsigned rT:7;
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} inst;
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};
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/**
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* Encode one output register with a 18-bit signed immediate
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*/
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union spe_inst_RI18 {
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uint32_t bits;
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struct {
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unsigned op:7;
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unsigned i18:18;
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unsigned rT:7;
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} inst;
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};
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/*@}*/
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static void
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indent(const struct spe_function *p)
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{
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int i;
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for (i = 0; i < p->indent; i++) {
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putchar(' ');
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}
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}
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static const char *
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rem_prefix(const char *longname)
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{
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return longname + 4;
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}
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static const char *
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reg_name(int reg)
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{
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switch (reg) {
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case SPE_REG_SP:
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return "$sp";
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case SPE_REG_RA:
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return "$lr";
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default:
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{
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/* cycle through four buffers to handle multiple calls per printf */
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static char buf[4][10];
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static int b = 0;
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b = (b + 1) % 4;
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sprintf(buf[b], "$%d", reg);
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return buf[b];
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}
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}
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}
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static void
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emit_instruction(struct spe_function *p, uint32_t inst_bits)
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{
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if (!p->store)
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return; /* out of memory, drop the instruction */
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if (p->num_inst == p->max_inst) {
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/* allocate larger buffer */
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uint32_t *newbuf;
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p->max_inst *= 2; /* 2x larger */
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newbuf = align_malloc(p->max_inst * SPE_INST_SIZE, 16);
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if (newbuf) {
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memcpy(newbuf, p->store, p->num_inst * SPE_INST_SIZE);
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}
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align_free(p->store);
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p->store = newbuf;
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if (!p->store) {
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/* out of memory */
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p->num_inst = 0;
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return;
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}
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}
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p->store[p->num_inst++] = inst_bits;
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}
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static void emit_RR(struct spe_function *p, unsigned op, int rT,
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int rA, int rB, const char *name)
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{
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union spe_inst_RR inst;
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inst.inst.op = op;
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inst.inst.rB = rB;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, %s, %s\n",
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rem_prefix(name), reg_name(rT), reg_name(rA), reg_name(rB));
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}
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}
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static void emit_RRR(struct spe_function *p, unsigned op, int rT,
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int rA, int rB, int rC, const char *name)
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{
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union spe_inst_RRR inst;
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inst.inst.op = op;
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inst.inst.rT = rT;
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inst.inst.rB = rB;
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inst.inst.rA = rA;
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inst.inst.rC = rC;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, %s, %s, %s\n", rem_prefix(name), reg_name(rT),
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reg_name(rA), reg_name(rB), reg_name(rC));
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}
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}
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static void emit_RI7(struct spe_function *p, unsigned op, int rT,
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int rA, int imm, const char *name)
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{
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union spe_inst_RI7 inst;
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inst.inst.op = op;
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inst.inst.i7 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, %s, 0x%x\n",
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rem_prefix(name), reg_name(rT), reg_name(rA), imm);
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}
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}
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static void emit_RI8(struct spe_function *p, unsigned op, int rT,
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int rA, int imm, const char *name)
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{
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union spe_inst_RI8 inst;
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inst.inst.op = op;
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inst.inst.i8 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, %s, 0x%x\n",
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rem_prefix(name), reg_name(rT), reg_name(rA), imm);
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}
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}
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static void emit_RI10(struct spe_function *p, unsigned op, int rT,
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int rA, int imm, const char *name)
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{
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union spe_inst_RI10 inst;
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inst.inst.op = op;
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inst.inst.i10 = imm;
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inst.inst.rA = rA;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, %s, 0x%x\n",
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rem_prefix(name), reg_name(rT), reg_name(rA), imm);
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}
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}
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/** As above, but do range checking on signed immediate value */
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static void emit_RI10s(struct spe_function *p, unsigned op, int rT,
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int rA, int imm, const char *name)
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{
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assert(imm <= 511);
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assert(imm >= -512);
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emit_RI10(p, op, rT, rA, imm, name);
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}
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static void emit_RI16(struct spe_function *p, unsigned op, int rT,
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int imm, const char *name)
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{
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union spe_inst_RI16 inst;
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inst.inst.op = op;
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inst.inst.i16 = imm;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
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}
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}
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static void emit_RI18(struct spe_function *p, unsigned op, int rT,
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int imm, const char *name)
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{
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union spe_inst_RI18 inst;
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inst.inst.op = op;
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inst.inst.i18 = imm;
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inst.inst.rT = rT;
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emit_instruction(p, inst.bits);
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if (p->print) {
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indent(p);
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printf("%s\t%s, 0x%x\n", rem_prefix(name), reg_name(rT), imm);
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}
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}
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#define EMIT(_name, _op) \
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void _name (struct spe_function *p) \
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{ \
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emit_RR(p, _op, 0, 0, 0, __FUNCTION__); \
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}
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#define EMIT_(_name, _op) \
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void _name (struct spe_function *p, int rT) \
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{ \
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emit_RR(p, _op, rT, 0, 0, __FUNCTION__); \
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}
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#define EMIT_R(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA) \
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{ \
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emit_RR(p, _op, rT, rA, 0, __FUNCTION__); \
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}
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#define EMIT_RR(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA, int rB) \
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{ \
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emit_RR(p, _op, rT, rA, rB, __FUNCTION__); \
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}
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#define EMIT_RRR(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA, int rB, int rC) \
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{ \
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emit_RRR(p, _op, rT, rA, rB, rC, __FUNCTION__); \
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}
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#define EMIT_RI7(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA, int imm) \
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{ \
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emit_RI7(p, _op, rT, rA, imm, __FUNCTION__); \
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}
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#define EMIT_RI8(_name, _op, bias) \
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void _name (struct spe_function *p, int rT, int rA, int imm) \
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{ \
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emit_RI8(p, _op, rT, rA, bias - imm, __FUNCTION__); \
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}
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#define EMIT_RI10(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA, int imm) \
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{ \
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emit_RI10(p, _op, rT, rA, imm, __FUNCTION__); \
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}
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#define EMIT_RI10s(_name, _op) \
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void _name (struct spe_function *p, int rT, int rA, int imm) \
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{ \
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emit_RI10s(p, _op, rT, rA, imm, __FUNCTION__); \
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}
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#define EMIT_RI16(_name, _op) \
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void _name (struct spe_function *p, int rT, int imm) \
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{ \
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emit_RI16(p, _op, rT, imm, __FUNCTION__); \
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}
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#define EMIT_RI18(_name, _op) \
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void _name (struct spe_function *p, int rT, int imm) \
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{ \
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emit_RI18(p, _op, rT, imm, __FUNCTION__); \
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}
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#define EMIT_I16(_name, _op) \
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void _name (struct spe_function *p, int imm) \
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{ \
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emit_RI16(p, _op, 0, imm, __FUNCTION__); \
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}
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#include "rtasm_ppc_spe.h"
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/**
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* Initialize an spe_function.
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* \param code_size initial size of instruction buffer to allocate, in bytes.
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* If zero, use a default.
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*/
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void spe_init_func(struct spe_function *p, unsigned code_size)
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{
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uint i;
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if (!code_size)
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code_size = 64;
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p->num_inst = 0;
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p->max_inst = code_size / SPE_INST_SIZE;
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p->store = align_malloc(code_size, 16);
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p->set_count = 0;
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memset(p->regs, 0, SPE_NUM_REGS * sizeof(p->regs[0]));
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/* Conservatively treat R0 - R2 and R80 - R127 as non-volatile.
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*/
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p->regs[0] = p->regs[1] = p->regs[2] = 1;
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for (i = 80; i <= 127; i++) {
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p->regs[i] = 1;
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}
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p->print = FALSE;
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p->indent = 0;
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}
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void spe_release_func(struct spe_function *p)
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{
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assert(p->num_inst <= p->max_inst);
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if (p->store != NULL) {
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align_free(p->store);
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}
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p->store = NULL;
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}
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/** Return current code size in bytes. */
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unsigned spe_code_size(const struct spe_function *p)
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{
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return p->num_inst * SPE_INST_SIZE;
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}
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/**
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* Allocate a SPE register.
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* \return register index or -1 if none left.
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*/
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int spe_allocate_available_register(struct spe_function *p)
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{
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unsigned i;
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for (i = 0; i < SPE_NUM_REGS; i++) {
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if (p->regs[i] == 0) {
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p->regs[i] = 1;
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return i;
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}
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}
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return -1;
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}
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/**
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* Mark the given SPE register as "allocated".
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*/
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int spe_allocate_register(struct spe_function *p, int reg)
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{
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assert(reg < SPE_NUM_REGS);
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assert(p->regs[reg] == 0);
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p->regs[reg] = 1;
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return reg;
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}
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/**
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* Mark the given SPE register as "unallocated". Note that this should
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* only be used on registers allocated in the current register set; an
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* assertion will fail if an attempt is made to deallocate a register
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* allocated in an earlier register set.
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*/
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void spe_release_register(struct spe_function *p, int reg)
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{
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assert(reg >= 0);
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assert(reg < SPE_NUM_REGS);
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assert(p->regs[reg] == 1);
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p->regs[reg] = 0;
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}
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/**
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* Start a new set of registers. This can be called if
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* it will be difficult later to determine exactly what
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* registers were actually allocated during a code generation
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* sequence, and you really just want to deallocate all of them.
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*/
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void spe_allocate_register_set(struct spe_function *p)
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{
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uint i;
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/* Keep track of the set count. If it ever wraps around to 0,
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* we're in trouble.
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*/
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p->set_count++;
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assert(p->set_count > 0);
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/* Increment the allocation count of all registers currently
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* allocated. Then any registers that are allocated in this set
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* will be the only ones with a count of 1; they'll all be released
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* when the register set is released.
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*/
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for (i = 0; i < SPE_NUM_REGS; i++) {
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if (p->regs[i] > 0)
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p->regs[i]++;
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}
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}
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void spe_release_register_set(struct spe_function *p)
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{
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uint i;
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/* If the set count drops below zero, we're in trouble. */
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assert(p->set_count > 0);
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p->set_count--;
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/* Drop the allocation level of all registers. Any allocated
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* during this register set will drop to 0 and then become
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* available.
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*/
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for (i = 0; i < SPE_NUM_REGS; i++) {
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if (p->regs[i] > 0)
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p->regs[i]--;
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}
|
|
}
|
|
|
|
|
|
unsigned
|
|
spe_get_registers_used(const struct spe_function *p, ubyte used[])
|
|
{
|
|
unsigned i, num = 0;
|
|
/* only count registers in the range available to callers */
|
|
for (i = 2; i < 80; i++) {
|
|
if (p->regs[i]) {
|
|
used[num++] = i;
|
|
}
|
|
}
|
|
return num;
|
|
}
|
|
|
|
|
|
void
|
|
spe_print_code(struct spe_function *p, boolean enable)
|
|
{
|
|
p->print = enable;
|
|
}
|
|
|
|
|
|
void
|
|
spe_indent(struct spe_function *p, int spaces)
|
|
{
|
|
p->indent += spaces;
|
|
}
|
|
|
|
|
|
void
|
|
spe_comment(struct spe_function *p, int rel_indent, const char *s)
|
|
{
|
|
if (p->print) {
|
|
p->indent += rel_indent;
|
|
indent(p);
|
|
p->indent -= rel_indent;
|
|
printf("# %s\n", s);
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Load quad word.
|
|
* NOTE: offset is in bytes and the least significant 4 bits must be zero!
|
|
*/
|
|
void spe_lqd(struct spe_function *p, int rT, int rA, int offset)
|
|
{
|
|
const boolean pSave = p->print;
|
|
|
|
/* offset must be a multiple of 16 */
|
|
assert(offset % 16 == 0);
|
|
/* offset must fit in 10-bit signed int field, after shifting */
|
|
assert((offset >> 4) <= 511);
|
|
assert((offset >> 4) >= -512);
|
|
|
|
p->print = FALSE;
|
|
emit_RI10(p, 0x034, rT, rA, offset >> 4, "spe_lqd");
|
|
p->print = pSave;
|
|
|
|
if (p->print) {
|
|
indent(p);
|
|
printf("lqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* Store quad word.
|
|
* NOTE: offset is in bytes and the least significant 4 bits must be zero!
|
|
*/
|
|
void spe_stqd(struct spe_function *p, int rT, int rA, int offset)
|
|
{
|
|
const boolean pSave = p->print;
|
|
|
|
/* offset must be a multiple of 16 */
|
|
assert(offset % 16 == 0);
|
|
/* offset must fit in 10-bit signed int field, after shifting */
|
|
assert((offset >> 4) <= 511);
|
|
assert((offset >> 4) >= -512);
|
|
|
|
p->print = FALSE;
|
|
emit_RI10(p, 0x024, rT, rA, offset >> 4, "spe_stqd");
|
|
p->print = pSave;
|
|
|
|
if (p->print) {
|
|
indent(p);
|
|
printf("stqd\t%s, %d(%s)\n", reg_name(rT), offset, reg_name(rA));
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* For branch instructions:
|
|
* \param d if 1, disable interupts if branch is taken
|
|
* \param e if 1, enable interupts if branch is taken
|
|
* If d and e are both zero, don't change interupt status (right?)
|
|
*/
|
|
|
|
/** Branch Indirect to address in rA */
|
|
void spe_bi(struct spe_function *p, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x1a8, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Interupt Return */
|
|
void spe_iret(struct spe_function *p, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x1aa, 0, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect and set link on external data */
|
|
void spe_bisled(struct spe_function *p, int rT, int rA, int d,
|
|
int e)
|
|
{
|
|
emit_RI7(p, 0x1ab, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect and set link. Save PC in rT, jump to rA. */
|
|
void spe_bisl(struct spe_function *p, int rT, int rA, int d,
|
|
int e)
|
|
{
|
|
emit_RI7(p, 0x1a9, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect if zero word. If rT.word[0]==0, jump to rA. */
|
|
void spe_biz(struct spe_function *p, int rT, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x128, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect if non-zero word. If rT.word[0]!=0, jump to rA. */
|
|
void spe_binz(struct spe_function *p, int rT, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x129, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect if zero halfword. If rT.halfword[1]==0, jump to rA. */
|
|
void spe_bihz(struct spe_function *p, int rT, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x12a, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
/** Branch indirect if non-zero halfword. If rT.halfword[1]!=0, jump to rA. */
|
|
void spe_bihnz(struct spe_function *p, int rT, int rA, int d, int e)
|
|
{
|
|
emit_RI7(p, 0x12b, rT, rA, (d << 5) | (e << 4), __FUNCTION__);
|
|
}
|
|
|
|
|
|
/* Hint-for-branch instructions
|
|
*/
|
|
#if 0
|
|
hbr;
|
|
hbra;
|
|
hbrr;
|
|
#endif
|
|
|
|
|
|
/* Control instructions
|
|
*/
|
|
#if 0
|
|
stop;
|
|
EMIT_RR (spe_stopd, 0x140);
|
|
EMIT_ (spe_nop, 0x201);
|
|
sync;
|
|
EMIT_ (spe_dsync, 0x003);
|
|
EMIT_R (spe_mfspr, 0x00c);
|
|
EMIT_R (spe_mtspr, 0x10c);
|
|
#endif
|
|
|
|
|
|
/**
|
|
** Helper / "macro" instructions.
|
|
** Use somewhat verbose names as a reminder that these aren't native
|
|
** SPE instructions.
|
|
**/
|
|
|
|
|
|
void
|
|
spe_load_float(struct spe_function *p, int rT, float x)
|
|
{
|
|
if (x == 0.0f) {
|
|
spe_il(p, rT, 0x0);
|
|
}
|
|
else if (x == 0.5f) {
|
|
spe_ilhu(p, rT, 0x3f00);
|
|
}
|
|
else if (x == 1.0f) {
|
|
spe_ilhu(p, rT, 0x3f80);
|
|
}
|
|
else if (x == -1.0f) {
|
|
spe_ilhu(p, rT, 0xbf80);
|
|
}
|
|
else {
|
|
union {
|
|
float f;
|
|
unsigned u;
|
|
} bits;
|
|
bits.f = x;
|
|
spe_ilhu(p, rT, bits.u >> 16);
|
|
spe_iohl(p, rT, bits.u & 0xffff);
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
spe_load_int(struct spe_function *p, int rT, int i)
|
|
{
|
|
if (-32768 <= i && i <= 32767) {
|
|
spe_il(p, rT, i);
|
|
}
|
|
else {
|
|
spe_ilhu(p, rT, i >> 16);
|
|
if (i & 0xffff)
|
|
spe_iohl(p, rT, i & 0xffff);
|
|
}
|
|
}
|
|
|
|
void spe_load_uint(struct spe_function *p, int rT, uint ui)
|
|
{
|
|
/* If the whole value is in the lower 18 bits, use ila, which
|
|
* doesn't sign-extend. Otherwise, if the two halfwords of
|
|
* the constant are identical, use ilh. Otherwise, if every byte of
|
|
* the desired value is 0x00 or 0xff, we can use Form Select Mask for
|
|
* Bytes Immediate (fsmbi) to load the value in a single instruction.
|
|
* Otherwise, in the general case, we have to use ilhu followed by iohl.
|
|
*/
|
|
if ((ui & 0x0003ffff) == ui) {
|
|
spe_ila(p, rT, ui);
|
|
}
|
|
else if ((ui >> 16) == (ui & 0xffff)) {
|
|
spe_ilh(p, rT, ui & 0xffff);
|
|
}
|
|
else if (
|
|
((ui & 0x000000ff) == 0 || (ui & 0x000000ff) == 0x000000ff) &&
|
|
((ui & 0x0000ff00) == 0 || (ui & 0x0000ff00) == 0x0000ff00) &&
|
|
((ui & 0x00ff0000) == 0 || (ui & 0x00ff0000) == 0x00ff0000) &&
|
|
((ui & 0xff000000) == 0 || (ui & 0xff000000) == 0xff000000)
|
|
) {
|
|
uint mask = 0;
|
|
/* fsmbi duplicates each bit in the given mask eight times,
|
|
* using a 16-bit value to initialize a 16-byte quadword.
|
|
* Each 4-bit nybble of the mask corresponds to a full word
|
|
* of the result; look at the value and figure out the mask
|
|
* (replicated for each word in the quadword), and then
|
|
* form the "select mask" to get the value.
|
|
*/
|
|
if ((ui & 0x000000ff) == 0x000000ff) mask |= 0x1111;
|
|
if ((ui & 0x0000ff00) == 0x0000ff00) mask |= 0x2222;
|
|
if ((ui & 0x00ff0000) == 0x00ff0000) mask |= 0x4444;
|
|
if ((ui & 0xff000000) == 0xff000000) mask |= 0x8888;
|
|
spe_fsmbi(p, rT, mask);
|
|
}
|
|
else {
|
|
/* The general case: this usually uses two instructions, but
|
|
* may use only one if the low-order 16 bits of each word are 0.
|
|
*/
|
|
spe_ilhu(p, rT, ui >> 16);
|
|
if (ui & 0xffff)
|
|
spe_iohl(p, rT, ui & 0xffff);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* This function is constructed identically to spe_xor_uint() below.
|
|
* Changes to one should be made in the other.
|
|
*/
|
|
void
|
|
spe_and_uint(struct spe_function *p, int rT, int rA, uint ui)
|
|
{
|
|
/* If we can, emit a single instruction, either And Byte Immediate
|
|
* (which uses the same constant across each byte), And Halfword Immediate
|
|
* (which sign-extends a 10-bit immediate to 16 bits and uses that
|
|
* across each halfword), or And Word Immediate (which sign-extends
|
|
* a 10-bit immediate to 32 bits).
|
|
*
|
|
* Otherwise, we'll need to use a temporary register.
|
|
*/
|
|
uint tmp;
|
|
|
|
/* If the upper 23 bits are all 0s or all 1s, sign extension
|
|
* will work and we can use And Word Immediate
|
|
*/
|
|
tmp = ui & 0xfffffe00;
|
|
if (tmp == 0xfffffe00 || tmp == 0) {
|
|
spe_andi(p, rT, rA, ui & 0x000003ff);
|
|
return;
|
|
}
|
|
|
|
/* If the ui field is symmetric along halfword boundaries and
|
|
* the upper 7 bits of each halfword are all 0s or 1s, we
|
|
* can use And Halfword Immediate
|
|
*/
|
|
tmp = ui & 0xfe00fe00;
|
|
if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
|
|
spe_andhi(p, rT, rA, ui & 0x000003ff);
|
|
return;
|
|
}
|
|
|
|
/* If the ui field is symmetric in each byte, then we can use
|
|
* the And Byte Immediate instruction.
|
|
*/
|
|
tmp = ui & 0x000000ff;
|
|
if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
|
|
spe_andbi(p, rT, rA, tmp);
|
|
return;
|
|
}
|
|
|
|
/* Otherwise, we'll have to use a temporary register. */
|
|
int tmp_reg = spe_allocate_available_register(p);
|
|
spe_load_uint(p, tmp_reg, ui);
|
|
spe_and(p, rT, rA, tmp_reg);
|
|
spe_release_register(p, tmp_reg);
|
|
}
|
|
|
|
|
|
/**
|
|
* This function is constructed identically to spe_and_uint() above.
|
|
* Changes to one should be made in the other.
|
|
*/
|
|
void
|
|
spe_xor_uint(struct spe_function *p, int rT, int rA, uint ui)
|
|
{
|
|
/* If we can, emit a single instruction, either Exclusive Or Byte
|
|
* Immediate (which uses the same constant across each byte), Exclusive
|
|
* Or Halfword Immediate (which sign-extends a 10-bit immediate to
|
|
* 16 bits and uses that across each halfword), or Exclusive Or Word
|
|
* Immediate (which sign-extends a 10-bit immediate to 32 bits).
|
|
*
|
|
* Otherwise, we'll need to use a temporary register.
|
|
*/
|
|
uint tmp;
|
|
|
|
/* If the upper 23 bits are all 0s or all 1s, sign extension
|
|
* will work and we can use Exclusive Or Word Immediate
|
|
*/
|
|
tmp = ui & 0xfffffe00;
|
|
if (tmp == 0xfffffe00 || tmp == 0) {
|
|
spe_xori(p, rT, rA, ui & 0x000003ff);
|
|
return;
|
|
}
|
|
|
|
/* If the ui field is symmetric along halfword boundaries and
|
|
* the upper 7 bits of each halfword are all 0s or 1s, we
|
|
* can use Exclusive Or Halfword Immediate
|
|
*/
|
|
tmp = ui & 0xfe00fe00;
|
|
if ((tmp == 0xfe00fe00 || tmp == 0) && ((ui >> 16) == (ui & 0x0000ffff))) {
|
|
spe_xorhi(p, rT, rA, ui & 0x000003ff);
|
|
return;
|
|
}
|
|
|
|
/* If the ui field is symmetric in each byte, then we can use
|
|
* the Exclusive Or Byte Immediate instruction.
|
|
*/
|
|
tmp = ui & 0x000000ff;
|
|
if ((ui >> 24) == tmp && ((ui >> 16) & 0xff) == tmp && ((ui >> 8) & 0xff) == tmp) {
|
|
spe_xorbi(p, rT, rA, tmp);
|
|
return;
|
|
}
|
|
|
|
/* Otherwise, we'll have to use a temporary register. */
|
|
int tmp_reg = spe_allocate_available_register(p);
|
|
spe_load_uint(p, tmp_reg, ui);
|
|
spe_xor(p, rT, rA, tmp_reg);
|
|
spe_release_register(p, tmp_reg);
|
|
}
|
|
|
|
void
|
|
spe_compare_equal_uint(struct spe_function *p, int rT, int rA, uint ui)
|
|
{
|
|
/* If the comparison value is 9 bits or less, it fits inside a
|
|
* Compare Equal Word Immediate instruction.
|
|
*/
|
|
if ((ui & 0x000001ff) == ui) {
|
|
spe_ceqi(p, rT, rA, ui);
|
|
}
|
|
/* Otherwise, we're going to have to load a word first. */
|
|
else {
|
|
int tmp_reg = spe_allocate_available_register(p);
|
|
spe_load_uint(p, tmp_reg, ui);
|
|
spe_ceq(p, rT, rA, tmp_reg);
|
|
spe_release_register(p, tmp_reg);
|
|
}
|
|
}
|
|
|
|
void
|
|
spe_compare_greater_uint(struct spe_function *p, int rT, int rA, uint ui)
|
|
{
|
|
/* If the comparison value is 10 bits or less, it fits inside a
|
|
* Compare Logical Greater Than Word Immediate instruction.
|
|
*/
|
|
if ((ui & 0x000003ff) == ui) {
|
|
spe_clgti(p, rT, rA, ui);
|
|
}
|
|
/* Otherwise, we're going to have to load a word first. */
|
|
else {
|
|
int tmp_reg = spe_allocate_available_register(p);
|
|
spe_load_uint(p, tmp_reg, ui);
|
|
spe_clgt(p, rT, rA, tmp_reg);
|
|
spe_release_register(p, tmp_reg);
|
|
}
|
|
}
|
|
|
|
void
|
|
spe_splat(struct spe_function *p, int rT, int rA)
|
|
{
|
|
/* Use a temporary, just in case rT == rA */
|
|
int tmp_reg = spe_allocate_available_register(p);
|
|
/* Duplicate bytes 0, 1, 2, and 3 across the whole register */
|
|
spe_ila(p, tmp_reg, 0x00010203);
|
|
spe_shufb(p, rT, rA, rA, tmp_reg);
|
|
spe_release_register(p, tmp_reg);
|
|
}
|
|
|
|
|
|
void
|
|
spe_complement(struct spe_function *p, int rT, int rA)
|
|
{
|
|
spe_nor(p, rT, rA, rA);
|
|
}
|
|
|
|
|
|
void
|
|
spe_move(struct spe_function *p, int rT, int rA)
|
|
{
|
|
/* Use different instructions depending on the instruction address
|
|
* to take advantage of the dual pipelines.
|
|
*/
|
|
if (p->num_inst & 1)
|
|
spe_shlqbyi(p, rT, rA, 0); /* odd pipe */
|
|
else
|
|
spe_ori(p, rT, rA, 0); /* even pipe */
|
|
}
|
|
|
|
|
|
void
|
|
spe_zero(struct spe_function *p, int rT)
|
|
{
|
|
spe_xor(p, rT, rT, rT);
|
|
}
|
|
|
|
|
|
void
|
|
spe_splat_word(struct spe_function *p, int rT, int rA, int word)
|
|
{
|
|
assert(word >= 0);
|
|
assert(word <= 3);
|
|
|
|
if (word == 0) {
|
|
int tmp1 = rT;
|
|
spe_ila(p, tmp1, 66051);
|
|
spe_shufb(p, rT, rA, rA, tmp1);
|
|
}
|
|
else {
|
|
/* XXX review this, we may not need the rotqbyi instruction */
|
|
int tmp1 = rT;
|
|
int tmp2 = spe_allocate_available_register(p);
|
|
|
|
spe_ila(p, tmp1, 66051);
|
|
spe_rotqbyi(p, tmp2, rA, 4 * word);
|
|
spe_shufb(p, rT, tmp2, tmp2, tmp1);
|
|
|
|
spe_release_register(p, tmp2);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* For each 32-bit float element of rA and rB, choose the smaller of the
|
|
* two, compositing them into the rT register.
|
|
*
|
|
* The Float Compare Greater Than (fcgt) instruction will put 1s into
|
|
* compare_reg where rA > rB, and 0s where rA <= rB.
|
|
*
|
|
* Then the Select Bits (selb) instruction will take bits from rA where
|
|
* compare_reg is 0, and from rB where compare_reg is 1; i.e., from rA
|
|
* where rA <= rB and from rB where rB > rA, which is exactly the
|
|
* "min" operation.
|
|
*
|
|
* The compare_reg could in many cases be the same as rT, unless
|
|
* rT == rA || rt == rB. But since this is common in constructions
|
|
* like "x = min(x, a)", we always allocate a new register to be safe.
|
|
*/
|
|
void
|
|
spe_float_min(struct spe_function *p, int rT, int rA, int rB)
|
|
{
|
|
int compare_reg = spe_allocate_available_register(p);
|
|
spe_fcgt(p, compare_reg, rA, rB);
|
|
spe_selb(p, rT, rA, rB, compare_reg);
|
|
spe_release_register(p, compare_reg);
|
|
}
|
|
|
|
/**
|
|
* For each 32-bit float element of rA and rB, choose the greater of the
|
|
* two, compositing them into the rT register.
|
|
*
|
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* The logic is similar to that of spe_float_min() above; the only
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* difference is that the registers on spe_selb() have been reversed,
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* so that the larger of the two is selected instead of the smaller.
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*/
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void
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spe_float_max(struct spe_function *p, int rT, int rA, int rB)
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{
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int compare_reg = spe_allocate_available_register(p);
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spe_fcgt(p, compare_reg, rA, rB);
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spe_selb(p, rT, rB, rA, compare_reg);
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spe_release_register(p, compare_reg);
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}
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#endif /* GALLIUM_CELL */
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