Alyssa Rosenzweig 5f5fda147a agx: use util_lut2 ... While Intel will use the full feature set of util_lut3 in the future, AGX can use the cut down 2-source versions right now to get us an in-tree user. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com> Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37200>		2025-09-16 21:48:37 +00:00
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clc	asahi/clc: promote bindless textures	2025-07-10 14:55:18 -04:00
compiler	agx: use util_lut2	2025-09-16 21:48:37 +00:00
drm-shim	asahi: fix drm-shim	2025-09-15 22:46:21 +00:00
genxml	asahi: reduce ppp alignment	2025-08-08 10:10:58 +00:00
isa	agx: fix simd reduce forcing no cache bit	2025-08-03 14:40:54 -04:00
layout	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
lib	asahi: enable virtgpu support	2025-08-06 11:11:06 +00:00
libagx	nir, asahi: commonize interleave_agx	2025-09-16 18:26:12 +00:00
vulkan	hk: Advertise VK_KHR_maintenance9	2025-09-16 17:36:58 +00:00
.clang-format	clang-format: Update the .clang-format files to conformance clang-format json-schema	2025-09-09 07:04:55 +00:00
meson.build	agx: add XML-based disassembler	2025-06-05 18:57:42 +00:00