Nanley Chery ea4de4ad3d anv: Don't ambiguate for undefined layouts on TGL+ ... For Tiger Lake and onward, we generally don't need to ambiguate the CCS before accessing it. This is safe for two reasons: - Tiger Lake and onward treat all CCS values as legal. - We enable compression on all writable image layouts. The CCS will receive all writes and will therefore always be valid. When dealing with modifiers, we continue to allow ambiguates in some instances. Before this patch, I found ~19.5k ambiguates in Wolfenstein: Youngblood's Riverside benchmark (note that this includes manually entering the benchmark and exiting the app). With this patch, the number of ambiguates goes down to zero. Improves performance of Fallout 4 at 1080p/High settings on Arc A380 by around 22%. Reviewed-by: Ivan Briano <ivan.briano@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20118>		2022-12-06 00:49:17 +00:00
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blorp	intel: factor out dispatch PS enabling logic	2022-12-06 00:37:47 +02:00
ci	ci: Add intel kbl xfail to flake	2022-11-30 17:24:03 +00:00
common	intel: Add SUPPORT_INTEL_INTEGRATED_GPUS build argument	2022-11-23 16:57:23 +00:00
compiler	intel: add missing restriction on fragment simd dispatch	2022-12-06 00:37:50 +02:00
dev	intel/dev: Add a has_illegal_ccs_values flag	2022-12-06 00:49:17 +00:00
ds	meson: do not use source_root() when possible	2022-11-22 06:11:07 +00:00
genxml	anv: refactor ray tracing dispatch	2022-12-02 09:28:23 +00:00
isl	isl: don't report I915_FORMAT_MOD_Y_TILED_CCS on Gfx8	2022-12-02 09:18:16 +00:00
nullhw-layer	utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*	2022-11-02 07:25:39 +00:00
perf	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00
tools	intel: Add SUPPORT_INTEL_INTEGRATED_GPUS build argument	2022-11-23 16:57:23 +00:00
vulkan	anv: Don't ambiguate for undefined layouts on TGL+	2022-12-06 00:49:17 +00:00
vulkan_hasvk	intel: factor out dispatch PS enabling logic	2022-12-06 00:37:47 +02:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00