Kenneth Graunke 424a6052df intel: Use a URB start offset of 0 for disabled stages. ... There are some cases where the VS is the only stage enabled, it uses the entire URB, and the URB is large enough that placing later stages after the VS exceeds the number of bits for "URB Starting Address". For example, on Icelake GT2, "varying-packing-simple mat2x4 array" from Piglit is getting a starting offset of 128 for the GS/HS/DS. But the field is only large enough to hold an offset of 127. i965 doesn't hit any genxml assertions because it's still using the old OUT_BATCH mechanism. 128 << GEN7_URB_STARTING_ADDRESS_SHIFT (57) == 0, with the extra bit falling off the end. So we place the disabled stage at the beginning of the URB (overlapping with push constants). This is likely okay since it's a zero size region (0 entries). It seems like the Vulkan driver might hit this assertion, however, and the situation seems harmless. To work around this, always place disabled stages at the start of the URB, so the last enabled stage can fill the remaining space without overflowing the field. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>		2018-11-03 23:25:57 -07:00
..
blorp	blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP	2018-10-26 16:39:35 -05:00
common	intel: Use a URB start offset of 0 for disabled stages.	2018-11-03 23:25:57 -07:00
compiler	intel/compiler: Stop assuming the entrypoint is called "main"	2018-10-30 20:14:52 -05:00
dev	intel: Introducing Whiskey Lake platform	2018-10-11 10:02:40 -07:00
genxml	anv/icl: Set Error Detection Behavior Control Bit in L3CNTLREG	2018-11-01 12:00:23 -07:00
isl	intel/isl: Add a unit suffixes to some struct fields and variables	2018-09-26 08:52:26 -05:00
tools	intel/tools: fix resource leak	2018-11-01 13:21:07 +00:00
vulkan	anv/icl: Disable prefetching of sampler state entries	2018-11-02 08:34:33 -07:00
Android.blorp.mk	intel: android: remove libdrm_intel requirement	2017-03-30 19:07:23 +01:00
Android.common.mk	android: link libmesa_intel_common with zlib and expat	2017-08-02 10:30:50 +03:00
Android.compiler.mk	android: fix build issues with brw_nir_trig_workarounds.c	2017-10-04 07:39:05 +03:00
Android.dev.mk	android: Use local i915_drm.h rather than the system one.	2018-03-23 10:05:02 -07:00
Android.genxml.mk	intel/genxml/icl: Generate packing headers	2018-02-15 16:14:55 -08:00
Android.isl.mk	intel/isl/icl: Build and use gen11 surface state emit functions	2018-02-15 16:14:55 -08:00
Android.mk	intel: Add missing includes for building on Android	2018-03-06 00:14:22 -08:00
Android.vulkan.mk	anv/android: we need git_sha1.h in include paths	2018-10-12 07:29:03 +03:00
Makefile.am	configure: allow building with python3	2018-10-31 19:15:50 +00:00
Makefile.blorp.am	blorp: automake: add TODO to the tarball	2017-02-24 17:37:00 +00:00
Makefile.common.am	automake: intel: correctly append to the LIBADD variable	2017-11-08 14:23:57 +00:00
Makefile.compiler.am	configure: allow building with python3	2018-10-31 19:15:50 +00:00
Makefile.dev.am	intel: Split gen_device_info out into libintel_dev	2018-03-05 09:47:37 -08:00
Makefile.genxml.am	intel: genxml: automake: include gen_bits_header.py in the tarball	2017-04-05 13:16:28 +01:00
Makefile.isl.am	intel/isl: Add format conversion code	2018-05-09 11:16:33 -07:00
Makefile.sources	intel/compiler: Do image load/store lowering to NIR	2018-08-29 14:04:02 -05:00
Makefile.tools.am	intel/tools: new i965_disasm tool	2018-08-29 11:19:55 -07:00
Makefile.vulkan.am	configure: allow building with python3	2018-10-31 19:15:50 +00:00
meson.build	intel: compiler option msse2 and mstackrealign	2018-09-07 13:45:46 +01:00