mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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527 lines
21 KiB
C
527 lines
21 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <string.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include "anv_private.h"
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#include "genxml/gen_macros.h"
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#include "genxml/genX_pack.h"
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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void
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gen7_cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer *cmd_buffer,
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uint32_t stages)
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{
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static const uint32_t sampler_state_opcodes[] = {
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[MESA_SHADER_VERTEX] = 43,
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[MESA_SHADER_TESS_CTRL] = 44, /* HS */
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[MESA_SHADER_TESS_EVAL] = 45, /* DS */
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[MESA_SHADER_GEOMETRY] = 46,
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[MESA_SHADER_FRAGMENT] = 47,
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[MESA_SHADER_COMPUTE] = 0,
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};
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static const uint32_t binding_table_opcodes[] = {
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[MESA_SHADER_VERTEX] = 38,
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[MESA_SHADER_TESS_CTRL] = 39,
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[MESA_SHADER_TESS_EVAL] = 40,
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[MESA_SHADER_GEOMETRY] = 41,
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[MESA_SHADER_FRAGMENT] = 42,
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[MESA_SHADER_COMPUTE] = 0,
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};
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anv_foreach_stage(s, stages) {
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if (cmd_buffer->state.samplers[s].alloc_size > 0) {
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS),
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._3DCommandSubOpcode = sampler_state_opcodes[s],
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.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset);
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}
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/* Always emit binding table pointers if we're asked to, since on SKL
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* this is what flushes push constants. */
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anv_batch_emit(&cmd_buffer->batch,
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GENX(3DSTATE_BINDING_TABLE_POINTERS_VS),
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._3DCommandSubOpcode = binding_table_opcodes[s],
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.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset);
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}
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}
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uint32_t
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gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer)
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{
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VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty &
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cmd_buffer->state.pipeline->active_stages;
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VkResult result = VK_SUCCESS;
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anv_foreach_stage(s, dirty) {
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result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
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&cmd_buffer->state.samplers[s]);
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if (result != VK_SUCCESS)
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break;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
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&cmd_buffer->state.binding_tables[s]);
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if (result != VK_SUCCESS)
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break;
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}
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if (result != VK_SUCCESS) {
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assert(result == VK_ERROR_OUT_OF_DEVICE_MEMORY);
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result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
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assert(result == VK_SUCCESS);
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/* Re-emit state base addresses so we get the new surface state base
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* address before we start emitting binding tables etc.
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*/
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anv_cmd_buffer_emit_state_base_address(cmd_buffer);
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/* Re-emit all active binding tables */
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dirty |= cmd_buffer->state.pipeline->active_stages;
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anv_foreach_stage(s, dirty) {
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result = anv_cmd_buffer_emit_samplers(cmd_buffer, s,
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&cmd_buffer->state.samplers[s]);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer, s,
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&cmd_buffer->state.binding_tables[s]);
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if (result != VK_SUCCESS)
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return result;
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}
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}
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cmd_buffer->state.descriptors_dirty &= ~dirty;
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return dirty;
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}
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#endif /* GEN_GEN == 7 && !GEN_IS_HASWELL */
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static inline int64_t
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clamp_int64(int64_t x, int64_t min, int64_t max)
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{
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if (x < min)
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return min;
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else if (x < max)
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return x;
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else
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return max;
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}
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#if GEN_GEN == 7 && !GEN_IS_HASWELL
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static void
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emit_scissor_state(struct anv_cmd_buffer *cmd_buffer,
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uint32_t count, const VkRect2D *scissors)
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{
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struct anv_state scissor_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, 32);
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for (uint32_t i = 0; i < count; i++) {
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const VkRect2D *s = &scissors[i];
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/* Since xmax and ymax are inclusive, we have to have xmax < xmin or
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* ymax < ymin for empty clips. In case clip x, y, width height are all
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* 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
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* what we want. Just special case empty clips and produce a canonical
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* empty clip. */
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static const struct GEN7_SCISSOR_RECT empty_scissor = {
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.ScissorRectangleYMin = 1,
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.ScissorRectangleXMin = 1,
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.ScissorRectangleYMax = 0,
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.ScissorRectangleXMax = 0
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};
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const int max = 0xffff;
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struct GEN7_SCISSOR_RECT scissor = {
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/* Do this math using int64_t so overflow gets clamped correctly. */
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.ScissorRectangleYMin = clamp_int64(s->offset.y, 0, max),
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.ScissorRectangleXMin = clamp_int64(s->offset.x, 0, max),
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.ScissorRectangleYMax = clamp_int64((uint64_t) s->offset.y + s->extent.height - 1, 0, max),
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.ScissorRectangleXMax = clamp_int64((uint64_t) s->offset.x + s->extent.width - 1, 0, max)
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};
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if (s->extent.width <= 0 || s->extent.height <= 0) {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
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&empty_scissor);
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} else {
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GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
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}
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}
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anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_SCISSOR_STATE_POINTERS,
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.ScissorRectPointer = scissor_state.offset);
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if (!cmd_buffer->device->info.has_llc)
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anv_state_clflush(scissor_state);
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}
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void
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gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
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{
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if (cmd_buffer->state.dynamic.scissor.count > 0) {
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emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count,
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cmd_buffer->state.dynamic.scissor.scissors);
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} else {
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/* Emit a default scissor based on the currently bound framebuffer */
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emit_scissor_state(cmd_buffer, 1,
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&(VkRect2D) {
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.offset = { .x = 0, .y = 0, },
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.extent = {
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.width = cmd_buffer->state.framebuffer->width,
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.height = cmd_buffer->state.framebuffer->height,
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},
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});
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}
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}
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#endif
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static const uint32_t vk_to_gen_index_type[] = {
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[VK_INDEX_TYPE_UINT16] = INDEX_WORD,
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[VK_INDEX_TYPE_UINT32] = INDEX_DWORD,
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};
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static const uint32_t restart_index_for_type[] = {
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[VK_INDEX_TYPE_UINT16] = UINT16_MAX,
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[VK_INDEX_TYPE_UINT32] = UINT32_MAX,
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};
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void genX(CmdBindIndexBuffer)(
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VkCommandBuffer commandBuffer,
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VkBuffer _buffer,
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VkDeviceSize offset,
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VkIndexType indexType)
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{
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ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
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ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
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cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
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if (GEN_IS_HASWELL)
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cmd_buffer->state.restart_index = restart_index_for_type[indexType];
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cmd_buffer->state.gen7.index_buffer = buffer;
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cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType];
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cmd_buffer->state.gen7.index_offset = offset;
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}
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static VkResult
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flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_device *device = cmd_buffer->device;
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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struct anv_state surfaces = { 0, }, samplers = { 0, };
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VkResult result;
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result = anv_cmd_buffer_emit_samplers(cmd_buffer,
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MESA_SHADER_COMPUTE, &samplers);
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if (result != VK_SUCCESS)
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return result;
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result = anv_cmd_buffer_emit_binding_table(cmd_buffer,
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MESA_SHADER_COMPUTE, &surfaces);
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if (result != VK_SUCCESS)
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return result;
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struct anv_state push_state = anv_cmd_buffer_cs_push_constants(cmd_buffer);
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
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unsigned local_id_dwords = cs_prog_data->local_invocation_id_regs * 8;
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unsigned push_constant_data_size =
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(prog_data->nr_params + local_id_dwords) * 4;
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unsigned reg_aligned_constant_size = ALIGN(push_constant_data_size, 32);
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unsigned push_constant_regs = reg_aligned_constant_size / 32;
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if (push_state.alloc_size) {
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD),
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.CURBETotalDataLength = push_state.alloc_size,
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.CURBEDataStartAddress = push_state.offset);
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}
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assert(prog_data->total_shared <= 64 * 1024);
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uint32_t slm_size = 0;
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if (prog_data->total_shared > 0) {
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/* slm_size is in 4k increments, but must be a power of 2. */
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slm_size = 4 * 1024;
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while (slm_size < prog_data->total_shared)
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slm_size <<= 1;
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slm_size /= 4 * 1024;
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}
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(INTERFACE_DESCRIPTOR_DATA), 64,
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.KernelStartPointer = pipeline->cs_simd,
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.BindingTablePointer = surfaces.offset,
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.SamplerStatePointer = samplers.offset,
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.ConstantURBEntryReadLength =
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push_constant_regs,
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#if !GEN_IS_HASWELL
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.ConstantURBEntryReadOffset = 0,
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#endif
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.BarrierEnable = cs_prog_data->uses_barrier,
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.SharedLocalMemorySize = slm_size,
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.NumberofThreadsinGPGPUThreadGroup =
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pipeline->cs_thread_width_max);
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const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
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anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD),
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.InterfaceDescriptorTotalLength = size,
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.InterfaceDescriptorDataStartAddress = state.offset);
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return VK_SUCCESS;
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}
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static void
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emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
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{
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anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
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.RegisterOffset = reg,
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.DataDWord = imm);
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}
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#define GEN7_L3SQCREG1 0xb010
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#define GEN7_L3CNTLREG2 0xb020
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#define GEN7_L3CNTLREG3 0xb024
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void
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genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
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{
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/* References for GL state:
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*
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* - commits e307cfa..228d5a3
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* - src/mesa/drivers/dri/i965/gen7_l3_state.c
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*/
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uint32_t l3c2_val = enable_slm ?
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/* All = 0 ways; URB = 16 ways; DC and RO = 16; SLM = 1 */
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/*0x02040021*/0x010000a1 :
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/* All = 0 ways; URB = 32 ways; DC = 0; RO = 32; SLM = 0 */
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/*0x04080040*/0x02000030;
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bool changed = cmd_buffer->state.current_l3_config != l3c2_val;
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if (changed) {
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/* According to the hardware docs, the L3 partitioning can only be changed
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* while the pipeline is completely drained and the caches are flushed,
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* which involves a first PIPE_CONTROL flush which stalls the pipeline and
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* initiates invalidation of the relevant caches...
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
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.TextureCacheInvalidationEnable = true,
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.ConstantCacheInvalidationEnable = true,
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.InstructionCacheInvalidateEnable = true,
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.DCFlushEnable = true,
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.PostSyncOperation = NoWrite,
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.CommandStreamerStallEnable = true);
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/* ...followed by a second stalling flush which guarantees that
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* invalidation is complete when the L3 configuration registers are
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* modified.
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*/
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL),
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.DCFlushEnable = true,
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.PostSyncOperation = NoWrite,
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.CommandStreamerStallEnable = true);
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anv_finishme("write GEN7_L3SQCREG1");
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emit_lri(&cmd_buffer->batch, GEN7_L3CNTLREG2, l3c2_val);
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emit_lri(&cmd_buffer->batch, GEN7_L3CNTLREG3,
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enable_slm ? 0x00040810 : 0x00040410);
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cmd_buffer->state.current_l3_config = l3c2_val;
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}
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}
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void
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genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
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const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
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VkResult result;
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assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
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bool needs_slm = cs_prog_data->base.total_shared > 0;
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genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
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if (cmd_buffer->state.current_pipeline != GPGPU) {
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anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT),
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.PipelineSelection = GPGPU);
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cmd_buffer->state.current_pipeline = GPGPU;
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}
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if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
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anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
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if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) ||
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(cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) {
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/* FIXME: figure out descriptors for gen7 */
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result = flush_compute_descriptor_set(cmd_buffer);
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assert(result == VK_SUCCESS);
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cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE_BIT;
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}
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cmd_buffer->state.compute_dirty = 0;
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}
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void
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genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
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{
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struct anv_pipeline *pipeline = cmd_buffer->state.pipeline;
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
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ANV_CMD_DIRTY_RENDER_TARGETS |
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ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
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ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)) {
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const struct anv_image_view *iview =
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anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
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const struct anv_image *image = iview ? iview->image : NULL;
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const struct anv_format *anv_format =
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iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
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const bool has_depth = iview && anv_format->has_depth;
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const uint32_t depth_format = has_depth ?
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isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
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&image->depth_surface.isl) : D16_UNORM;
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uint32_t sf_dw[GENX(3DSTATE_SF_length)];
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struct GENX(3DSTATE_SF) sf = {
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GENX(3DSTATE_SF_header),
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.DepthBufferSurfaceFormat = depth_format,
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.LineWidth = cmd_buffer->state.dynamic.line_width,
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.GlobalDepthOffsetConstant = cmd_buffer->state.dynamic.depth_bias.bias,
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.GlobalDepthOffsetScale = cmd_buffer->state.dynamic.depth_bias.slope,
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.GlobalDepthOffsetClamp = cmd_buffer->state.dynamic.depth_bias.clamp
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};
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GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
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anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
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}
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if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
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ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
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struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
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struct anv_state cc_state =
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anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
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GENX(COLOR_CALC_STATE_length) * 4,
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64);
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struct GENX(COLOR_CALC_STATE) cc = {
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.BlendConstantColorRed = cmd_buffer->state.dynamic.blend_constants[0],
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.BlendConstantColorGreen = cmd_buffer->state.dynamic.blend_constants[1],
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.BlendConstantColorBlue = cmd_buffer->state.dynamic.blend_constants[2],
|
|
.BlendConstantColorAlpha = cmd_buffer->state.dynamic.blend_constants[3],
|
|
.StencilReferenceValue = d->stencil_reference.front & 0xff,
|
|
.BackFaceStencilReferenceValue = d->stencil_reference.back & 0xff,
|
|
};
|
|
GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
|
|
if (!cmd_buffer->device->info.has_llc)
|
|
anv_state_clflush(cc_state);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
GENX(3DSTATE_CC_STATE_POINTERS),
|
|
.ColorCalcStatePointer = cc_state.offset);
|
|
}
|
|
|
|
if (cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
|
ANV_CMD_DIRTY_RENDER_TARGETS |
|
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
|
|
ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK)) {
|
|
uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
|
|
struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
|
|
|
|
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
|
|
.StencilTestMask = d->stencil_compare_mask.front & 0xff,
|
|
.StencilWriteMask = d->stencil_write_mask.front & 0xff,
|
|
|
|
.BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
|
|
.BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
|
|
};
|
|
GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
|
|
|
|
struct anv_state ds_state =
|
|
anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
|
|
pipeline->gen7.depth_stencil_state,
|
|
GENX(DEPTH_STENCIL_STATE_length), 64);
|
|
|
|
anv_batch_emit(&cmd_buffer->batch,
|
|
GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS),
|
|
.PointertoDEPTH_STENCIL_STATE = ds_state.offset);
|
|
}
|
|
|
|
if (cmd_buffer->state.gen7.index_buffer &&
|
|
cmd_buffer->state.dirty & (ANV_CMD_DIRTY_PIPELINE |
|
|
ANV_CMD_DIRTY_INDEX_BUFFER)) {
|
|
struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer;
|
|
uint32_t offset = cmd_buffer->state.gen7.index_offset;
|
|
|
|
#if GEN_IS_HASWELL
|
|
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF,
|
|
.IndexedDrawCutIndexEnable = pipeline->primitive_restart,
|
|
.CutIndex = cmd_buffer->state.restart_index);
|
|
#endif
|
|
|
|
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER),
|
|
#if !GEN_IS_HASWELL
|
|
.CutIndexEnable = pipeline->primitive_restart,
|
|
#endif
|
|
.IndexFormat = cmd_buffer->state.gen7.index_type,
|
|
.MemoryObjectControlState = GENX(MOCS),
|
|
.BufferStartingAddress = { buffer->bo, buffer->offset + offset },
|
|
.BufferEndingAddress = { buffer->bo, buffer->offset + buffer->size });
|
|
}
|
|
|
|
cmd_buffer->state.dirty = 0;
|
|
}
|
|
|
|
void genX(CmdSetEvent)(
|
|
VkCommandBuffer commandBuffer,
|
|
VkEvent event,
|
|
VkPipelineStageFlags stageMask)
|
|
{
|
|
stub();
|
|
}
|
|
|
|
void genX(CmdResetEvent)(
|
|
VkCommandBuffer commandBuffer,
|
|
VkEvent event,
|
|
VkPipelineStageFlags stageMask)
|
|
{
|
|
stub();
|
|
}
|
|
|
|
void genX(CmdWaitEvents)(
|
|
VkCommandBuffer commandBuffer,
|
|
uint32_t eventCount,
|
|
const VkEvent* pEvents,
|
|
VkPipelineStageFlags srcStageMask,
|
|
VkPipelineStageFlags destStageMask,
|
|
uint32_t memoryBarrierCount,
|
|
const VkMemoryBarrier* pMemoryBarriers,
|
|
uint32_t bufferMemoryBarrierCount,
|
|
const VkBufferMemoryBarrier* pBufferMemoryBarriers,
|
|
uint32_t imageMemoryBarrierCount,
|
|
const VkImageMemoryBarrier* pImageMemoryBarriers)
|
|
{
|
|
stub();
|
|
}
|