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c9950786f6
Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23905>
126 lines
4.2 KiB
C
126 lines
4.2 KiB
C
/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef INTEL_GEM_H
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#define INTEL_GEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <sys/ioctl.h>
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#include "intel_engine.h"
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#include "util/macros.h"
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#define RCS_TIMESTAMP 0x2358
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static inline uint64_t
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intel_canonical_address(uint64_t v)
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{
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/* From the Broadwell PRM Vol. 2a, MI_LOAD_REGISTER_MEM::MemoryAddress:
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*
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* "This field specifies the address of the memory location where the
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* register value specified in the DWord above will read from. The
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* address specifies the DWord location of the data. Range =
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* GraphicsVirtualAddress[63:2] for a DWord register GraphicsAddress
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* [63:48] are ignored by the HW and assumed to be in correct
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* canonical form [63:48] == [47]."
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*/
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const int shift = 63 - 47;
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return (int64_t)(v << shift) >> shift;
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}
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/**
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* This returns a 48-bit address with the high 16 bits zeroed.
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*
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* It's the opposite of intel_canonicalize_address.
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*/
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static inline uint64_t
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intel_48b_address(uint64_t v)
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{
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const int shift = 63 - 47;
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return (uint64_t)(v << shift) >> shift;
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}
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/**
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* Call ioctl, restarting if it is interrupted
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*/
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static inline int
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intel_ioctl(int fd, unsigned long request, void *arg)
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{
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int ret;
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do {
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ret = ioctl(fd, request, arg);
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} while (ret == -1 && (errno == EINTR || errno == EAGAIN));
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return ret;
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}
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bool intel_gem_supports_syncobj_wait(int fd);
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bool
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intel_gem_read_render_timestamp(int fd, enum intel_kmd_type kmd_type,
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uint64_t *value);
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bool intel_gem_can_render_on_fd(int fd, enum intel_kmd_type kmd_type);
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/* Functions only used by i915 */
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enum intel_gem_create_context_flags {
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INTEL_GEM_CREATE_CONTEXT_EXT_RECOVERABLE_FLAG = BITFIELD_BIT(0),
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INTEL_GEM_CREATE_CONTEXT_EXT_PROTECTED_FLAG = BITFIELD_BIT(1),
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};
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bool intel_gem_create_context(int fd, uint32_t *context_id);
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bool intel_gem_destroy_context(int fd, uint32_t context_id);
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bool
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intel_gem_create_context_engines(int fd,
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enum intel_gem_create_context_flags flags,
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const struct intel_query_engine_info *info,
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int num_engines, enum intel_engine_class *engine_classes,
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uint32_t *context_id);
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bool
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intel_gem_set_context_param(int fd, uint32_t context, uint32_t param,
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uint64_t value);
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bool
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intel_gem_get_context_param(int fd, uint32_t context, uint32_t param,
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uint64_t *value);
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bool intel_gem_get_param(int fd, uint32_t param, int *value);
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bool intel_gem_wait_on_get_param(int fd, uint32_t param, int target_val,
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uint32_t timeout_ms);
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bool intel_gem_create_context_ext(int fd, enum intel_gem_create_context_flags flags,
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uint32_t *ctx_id);
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bool intel_gem_supports_protected_context(int fd,
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enum intel_kmd_type kmd_type);
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#ifdef __cplusplus
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}
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#endif
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#endif /* INTEL_GEM_H */
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