mesa/src/amd
Timur Kristóf 3fd002f6d5 radv, aco: Remove the code that jumped to RADV's TCS epilogs.
The actual TCS epilog selection code is kept unchanged for now,
we'll delete it when RadeonSI also gets rid of TCS epilogs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28 23:44:03 +00:00
..
addrlib amd: fix addrlib regression 2024-03-22 08:25:21 +00:00
ci radv/ci: another batch of flakes 2024-03-28 18:59:10 +00:00
common ac/nir/tess: Emit tess factor stores based on new intrinsics. 2024-03-28 23:44:03 +00:00
compiler radv, aco: Remove the code that jumped to RADV's TCS epilogs. 2024-03-28 23:44:03 +00:00
drm-shim amd: Use align64 instead of ALIGN for 64 bit value parameter 2024-01-03 22:02:17 +00:00
llvm ac/llvm: remove remnants of gfx10 NGG streamout 2024-03-22 21:58:02 +00:00
registers amd/registers: add correct gfx11.x enums for BINNING_MODE 2024-03-11 23:36:55 +00:00
vpelib radeonsi/vpe: support vpe 1.1 2024-03-25 00:59:02 +00:00
vulkan radv, aco: Remove the code that jumped to RADV's TCS epilogs. 2024-03-28 23:44:03 +00:00
meson.build amd,radeonsi: add libvpe 2023-12-01 00:23:38 +00:00