mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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f0cb8852a4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
326 lines
8.3 KiB
C
326 lines
8.3 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "ac_debug.h"
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#include "sid.h"
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#include "sid_tables.h"
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#include "util/u_string.h"
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#include <inttypes.h>
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const struct si_reg *ac_find_register(enum amd_gfx_level gfx_level, enum radeon_family family,
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unsigned offset)
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{
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const struct si_reg *table;
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unsigned table_size;
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switch (gfx_level) {
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case GFX11_5:
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table = gfx115_reg_table;
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table_size = ARRAY_SIZE(gfx115_reg_table);
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break;
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case GFX11:
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table = gfx11_reg_table;
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table_size = ARRAY_SIZE(gfx11_reg_table);
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break;
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case GFX10_3:
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case GFX10:
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table = gfx10_reg_table;
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table_size = ARRAY_SIZE(gfx10_reg_table);
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break;
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case GFX9:
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if (family == CHIP_GFX940) {
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table = gfx940_reg_table;
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table_size = ARRAY_SIZE(gfx940_reg_table);
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break;
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}
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table = gfx9_reg_table;
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table_size = ARRAY_SIZE(gfx9_reg_table);
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break;
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case GFX8:
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if (family == CHIP_STONEY) {
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table = gfx81_reg_table;
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table_size = ARRAY_SIZE(gfx81_reg_table);
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break;
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}
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table = gfx8_reg_table;
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table_size = ARRAY_SIZE(gfx8_reg_table);
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break;
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case GFX7:
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table = gfx7_reg_table;
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table_size = ARRAY_SIZE(gfx7_reg_table);
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break;
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case GFX6:
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table = gfx6_reg_table;
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table_size = ARRAY_SIZE(gfx6_reg_table);
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break;
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default:
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return NULL;
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}
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for (unsigned i = 0; i < table_size; i++) {
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const struct si_reg *reg = &table[i];
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if (reg->offset == offset)
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return reg;
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}
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return NULL;
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}
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const char *ac_get_register_name(enum amd_gfx_level gfx_level, enum radeon_family family,
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unsigned offset)
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{
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const struct si_reg *reg = ac_find_register(gfx_level, family, offset);
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return reg ? sid_strings + reg->name_offset : "(no name)";
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}
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bool ac_register_exists(enum amd_gfx_level gfx_level, enum radeon_family family,
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unsigned offset)
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{
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return ac_find_register(gfx_level, family, offset) != NULL;
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}
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/**
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* Parse dmesg and return TRUE if a VM fault has been detected.
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*
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* \param gfx_level gfx level
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* \param old_dmesg_timestamp previous dmesg timestamp parsed at init time
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* \param out_addr detected VM fault addr
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*/
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bool ac_vm_fault_occurred(enum amd_gfx_level gfx_level, uint64_t *old_dmesg_timestamp,
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uint64_t *out_addr)
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{
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#ifdef _WIN32
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return false;
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#else
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char line[2000];
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unsigned sec, usec;
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int progress = 0;
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uint64_t dmesg_timestamp = 0;
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bool fault = false;
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FILE *p = popen("dmesg", "r");
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if (!p)
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return false;
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while (fgets(line, sizeof(line), p)) {
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char *msg, len;
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if (!line[0] || line[0] == '\n')
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continue;
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/* Get the timestamp. */
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if (sscanf(line, "[%u.%u]", &sec, &usec) != 2) {
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static bool hit = false;
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if (!hit) {
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fprintf(stderr, "%s: failed to parse line '%s'\n", __func__, line);
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hit = true;
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}
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continue;
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}
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dmesg_timestamp = sec * 1000000ull + usec;
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/* If just updating the timestamp. */
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if (!out_addr)
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continue;
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/* Process messages only if the timestamp is newer. */
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if (dmesg_timestamp <= *old_dmesg_timestamp)
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continue;
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/* Only process the first VM fault. */
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if (fault)
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continue;
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/* Remove trailing \n */
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len = strlen(line);
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if (len && line[len - 1] == '\n')
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line[len - 1] = 0;
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/* Get the message part. */
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msg = strchr(line, ']');
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if (!msg)
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continue;
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msg++;
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const char *header_line, *addr_line_prefix, *addr_line_format;
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if (gfx_level >= GFX9) {
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/* Match this:
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* ..: [gfxhub] VMC page fault (src_id:0 ring:158 vm_id:2 pas_id:0)
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* ..: at page 0x0000000219f8f000 from 27
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* ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
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*/
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header_line = "VMC page fault";
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addr_line_prefix = " at page";
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addr_line_format = "%" PRIx64;
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} else {
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header_line = "GPU fault detected:";
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addr_line_prefix = "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
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addr_line_format = "%" PRIX64;
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}
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switch (progress) {
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case 0:
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if (strstr(msg, header_line))
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progress = 1;
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break;
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case 1:
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msg = strstr(msg, addr_line_prefix);
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if (msg) {
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msg = strstr(msg, "0x");
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if (msg) {
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msg += 2;
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if (sscanf(msg, addr_line_format, out_addr) == 1)
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fault = true;
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}
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}
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progress = 0;
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break;
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default:
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progress = 0;
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}
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}
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pclose(p);
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if (dmesg_timestamp > *old_dmesg_timestamp)
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*old_dmesg_timestamp = dmesg_timestamp;
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return fault;
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#endif
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}
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static int compare_wave(const void *p1, const void *p2)
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{
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struct ac_wave_info *w1 = (struct ac_wave_info *)p1;
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struct ac_wave_info *w2 = (struct ac_wave_info *)p2;
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/* Sort waves according to PC and then SE, SH, CU, etc. */
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if (w1->pc < w2->pc)
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return -1;
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if (w1->pc > w2->pc)
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return 1;
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if (w1->se < w2->se)
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return -1;
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if (w1->se > w2->se)
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return 1;
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if (w1->sh < w2->sh)
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return -1;
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if (w1->sh > w2->sh)
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return 1;
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if (w1->cu < w2->cu)
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return -1;
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if (w1->cu > w2->cu)
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return 1;
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if (w1->simd < w2->simd)
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return -1;
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if (w1->simd > w2->simd)
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return 1;
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if (w1->wave < w2->wave)
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return -1;
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if (w1->wave > w2->wave)
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return 1;
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return 0;
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}
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/* Return wave information. "waves" should be a large enough array. */
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unsigned ac_get_wave_info(enum amd_gfx_level gfx_level, const struct radeon_info *info,
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struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP])
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{
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#ifdef _WIN32
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return 0;
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#else
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char line[2000], cmd[256];
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unsigned num_waves = 0;
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sprintf(cmd, "umr --by-pci %04x:%02x:%02x.%01x -O halt_waves -wa %s",
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info->pci.domain, info->pci.bus, info->pci.dev, info->pci.func,
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gfx_level >= GFX10 ? "gfx_0.0.0" : "gfx");
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FILE *p = popen(cmd, "r");
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if (!p)
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return 0;
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if (!fgets(line, sizeof(line), p) || strncmp(line, "SE", 2) != 0) {
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pclose(p);
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return 0;
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}
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while (fgets(line, sizeof(line), p)) {
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struct ac_wave_info *w;
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uint32_t pc_hi, pc_lo, exec_hi, exec_lo;
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assert(num_waves < AC_MAX_WAVES_PER_CHIP);
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w = &waves[num_waves];
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if (sscanf(line, "%u %u %u %u %u %x %x %x %x %x %x %x", &w->se, &w->sh, &w->cu, &w->simd,
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&w->wave, &w->status, &pc_hi, &pc_lo, &w->inst_dw0, &w->inst_dw1, &exec_hi,
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&exec_lo) == 12) {
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w->pc = ((uint64_t)pc_hi << 32) | pc_lo;
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w->exec = ((uint64_t)exec_hi << 32) | exec_lo;
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w->matched = false;
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num_waves++;
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}
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}
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qsort(waves, num_waves, sizeof(struct ac_wave_info), compare_wave);
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pclose(p);
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return num_waves;
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#endif
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}
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/* List of GFXHUB clients from AMDGPU source code. */
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static const char *const gfx10_gfxhub_client_ids[] = {
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"CB/DB",
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"Reserved",
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"GE1",
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"GE2",
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"CPF",
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"CPC",
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"CPG",
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"RLC",
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"TCP",
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"SQC (inst)",
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"SQC (data)",
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"SQG",
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"Reserved",
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"SDMA0",
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"SDMA1",
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"GCR",
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"SDMA2",
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"SDMA3",
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};
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static const char *
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ac_get_gfx10_gfxhub_client(unsigned cid)
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{
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if (cid >= ARRAY_SIZE(gfx10_gfxhub_client_ids))
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return "UNKNOWN";
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return gfx10_gfxhub_client_ids[cid];
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}
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void ac_print_gpuvm_fault_status(FILE *output, enum amd_gfx_level gfx_level,
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uint32_t status)
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{
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if (gfx_level >= GFX10) {
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const uint8_t cid = G_00A130_CID(status);
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fprintf(output, "GCVM_L2_PROTECTION_FAULT_STATUS: 0x%x\n", status);
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fprintf(output, "\t CLIENT_ID: (%s) 0x%x\n", ac_get_gfx10_gfxhub_client(cid), cid);
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fprintf(output, "\t MORE_FAULTS: %d\n", G_00A130_MORE_FAULTS(status));
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fprintf(output, "\t WALKER_ERROR: %d\n", G_00A130_WALKER_ERROR(status));
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fprintf(output, "\t PERMISSION_FAULTS: %d\n", G_00A130_PERMISSION_FAULTS(status));
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fprintf(output, "\t MAPPING_ERROR: %d\n", G_00A130_MAPPING_ERROR(status));
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fprintf(output, "\t RW: %d\n", G_00A130_RW(status));
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} else {
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fprintf(output, "VM_CONTEXT1_PROTECTION_FAULT_STATUS: 0x%x\n", status);
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}
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}
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