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mesa/src/intel/common
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Ben Widawsky 3e1055591b i965/cnl: Add l3 configuration for Cannonlake 
V2 (Anuj):
Squash the changes in one patch rebase on master.
Address the review comments made by Francisco Jerez.
Do the URB allocation per slice (not per bank).

V3 (Anuj):
Update the comment.
Format the table as other l3 config tables.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
---
V1 was sent out with the heading:
"i965/cnl: Properly handle l3 configuration"
2017-06-20 12:18:26 -07:00
..
gen_debug.c i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_debug.h i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency. 2017-06-05 23:32:40 -07:00
gen_decoder.c intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_decoder.h intel: gen-decoder: rework how we handle groups 2017-06-06 14:04:37 +01:00
gen_device_info.c intel: common: add number of thread per eu 2017-06-19 22:11:00 +01:00
gen_device_info.h intel: common: add number of thread per eu 2017-06-19 22:11:00 +01:00
gen_l3_config.c i965/cnl: Add l3 configuration for Cannonlake 2017-06-20 12:18:26 -07:00
gen_l3_config.h intel: Share URB configuration code between GL and Vulkan. 2016-11-19 11:40:01 -08:00
gen_sample_positions.h intel/common: use correct header guards 2016-10-14 11:53:37 +01:00
gen_urb_config.c i965: Fix a mistake from porting the URB allocation code to arrays. 2016-11-23 16:57:29 -08:00