Sil Vilerino 3ab25d6fb3 pipe: Support inserting new headers on each H264/HEVC IDR frame ... Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26456>		2023-12-06 03:58:52 +00:00
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frontend	util/driconf: add workarounds for the Chronicles of Riddick	2023-08-24 22:38:56 +00:00
pipe	pipe: Support inserting new headers on each H264/HEVC IDR frame	2023-12-06 03:58:52 +00:00
winsys	radeonsi: limit CP DMA to skip holes in sparse bo	2023-08-18 15:42:20 +00:00