Lionel Landwerlin 37b3601052 intel/fs: switch register allocation spilling to use LSC on Gfx12.5+ ... v2: drop the hardcoded inst->mlen=1 (Rohan) v3: Move back to LOAD/STORE messages (limited to SIMD16 for LSC) v4: Also use 4 GRFs transpose loads for fills (Curro) v5: Reduce amount of needed register to build per lane offsets (Curro) Drop some now useless SIMD32 code Unify unspill code Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17555>		2022-08-24 17:51:40 +00:00
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blorp	intel/blorp: Set uses_sample_shading for MSAA blit shaders	2022-07-13 20:28:42 +00:00
ci	iris/ci: Set FDO_CI_CONCURRENT for all Chromebook jobs	2022-08-15 11:40:16 +02:00
common	anv: Do not duplicate intel_device_info memory in each logical device	2022-08-19 16:29:58 +00:00
compiler	intel/fs: switch register allocation spilling to use LSC on Gfx12.5+	2022-08-24 17:51:40 +00:00
dev	intel/compiler: Remove INTEL_DEBUG=tcs8	2022-08-24 00:39:57 +00:00
ds	intel/ds: Update to Perfetto API v28.0	2022-08-19 18:09:43 +00:00
genxml	genxml: Add BVH data structures	2022-08-05 11:51:31 +00:00
isl	anv: fixup assertions on lowered storage formats	2022-08-23 08:29:51 +00:00
nullhw-layer	intel/nullhw: Use correct macro to fix build regression	2022-08-01 10:54:38 +00:00
perf	intel: fix typos found by codespell	2022-06-27 10:20:55 +00:00
tools	intel/tools: Also look for 'batch' tag	2022-08-17 02:24:09 +00:00
vulkan	anv: convert assert into unreachable to avoid fallthrough error	2022-08-23 18:37:41 +00:00
meson.build	anv: add perfetto source	2022-01-14 20:17:44 +00:00