mesa/src/intel
Kenneth Graunke 4ed9fd62c9 anv: Lower bufferImageGranularity to 1 from 64
The Vulkan 1.3 spec says:

   "The implementation-dependent limit bufferImageGranularity specifies
    a page-like granularity at which linear and non-linear resources
    must be placed in adjacent memory locations to avoid aliasing.  Two
    resources which do not satisfy this granularity requirement are said
    to alias. bufferImageGranularity is specified in bytes, and must be
    a power of two.  Implementations which do not impose a granularity
    restriction may report a bufferImageGranularity value of one.

    Note: Despite its name, bufferImageGranularity is really a
    granularity between "linear" and "non-linear" resources."

We set this limit to 64 bytes (a cacheline) at the dawn of time, without
any real rationale attached.  There shouldn't be any restrictions here.
Our tile sizes are typically 4K, and tiled resource addresses are
aligned to the tile size, and the extent is also a multiple of the tile
sized.  So if a linear resource occurs before a tiled one, there will
naturally be some space due to the alignment of the tiled resource's
starting address.  If a linear resource occurs after a tiled one, the
tiled resource's ending address is already 4K aligned, which is already
guaranteeing that they won't share a cacheline.

So I think it should be fine to reduce this to 1.  The other Vulkan
driver for our hardware seems to advertise 1 here as well.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15066>
2022-02-18 09:52:00 +00:00
..
blorp blorp: Assert that blorp_copy() on the blitter can handle it 2022-02-07 09:50:01 -08:00
ci ci: Bump VK-GL-CTS to 1.3.1.0. 2022-02-08 22:16:36 +00:00
common intel: Add missing dep of gen_*_header.py on utils.py. 2022-02-02 11:21:57 -08:00
compiler nir: Add missing dependency on nir_opcodes.py 2022-02-17 22:57:33 +00:00
dev intel/dev: provide some default values for no_hw 2022-02-17 07:49:08 +00:00
ds intel/ds: fix compilation with perfetto 2022-02-08 12:29:21 +00:00
genxml intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation 2022-02-09 10:05:10 +00:00
isl intel/isl: Add format assertions for surfaces using CCS 2022-02-10 04:47:14 +00:00
nullhw-layer intel/nullhw: fix build 2021-03-26 20:12:40 +00:00
perf intel/perf: use a function to do common allocations 2022-01-20 06:41:17 +00:00
tools intel: remove chipset_id 2022-01-13 03:09:36 +00:00
vulkan anv: Lower bufferImageGranularity to 1 from 64 2022-02-18 09:52:00 +00:00
Makefile.perf.am intel: Rename GEN_PERF prefix to INTEL_PERF in build files 2021-04-20 20:06:34 +00:00
meson.build anv: add perfetto source 2022-01-14 20:17:44 +00:00