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35c76bc7f7
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35195>
101 lines
3.9 KiB
C
101 lines
3.9 KiB
C
/*
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* Copyright © 2024 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Marek Olšák <marek.olsak@amd.com>
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*
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*/
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#ifndef NIR_TCS_INFO_H
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#define NIR_TCS_INFO_H
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#include "compiler/shader_enums.h"
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#include "nir_defines.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct nir_tcs_info {
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/* The bitmask of patch outputs that are always written by all invocations
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* in all execution paths.
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*
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* This is useful when a pass wants to read patch output values at the end
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* of the shader. If this is true, the pass doesn't have to insert a barrier
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* and use output loads, it can just use the SSA defs that are being stored
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* (or phis thereof) to get the patch output values.
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*/
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uint32_t patch_outputs_defined_by_all_invoc;
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/* The bitmask of patch outputs that are only written by invocation 0. */
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uint32_t patch_outputs_only_written_by_invoc0;
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/* The bitmask of patch outputs that are only read by invocation 0. */
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uint32_t patch_outputs_only_read_by_invoc0;
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/* The bitmask of tess level outputs that are written by all invocations.
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* Bit 0 is outer levels, bit 1 is inner levels.
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*/
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uint8_t tess_levels_defined_by_all_invoc : 2;
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/* The bitmask of tess level outputs that are only written by invocation 0. */
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uint8_t tess_levels_only_written_by_invoc0 : 2;
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/* The bitmask of tess level outputs that are only read by invocation 0. */
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uint8_t tess_levels_only_read_by_invoc0 : 2;
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/* Whether all tess levels that are written in all invocations. */
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bool all_invocations_define_tess_levels : 1;
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/* Whether any of the outer tess level components is effectively 0, meaning
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* that the shader discards the patch. NaNs and negative values are included
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* in this. If the patch is discarded, inner tess levels have no effect.
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*/
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bool all_tess_levels_are_effectively_zero : 1;
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/* Whether all tess levels are effectively 1, meaning that the tessellator
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* behaves as if they were 1. There is a range of values that lead to that
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* behavior depending on the tessellation spacing.
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*/
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bool all_tess_levels_are_effectively_one : 1;
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/* Whether the shader uses a barrier synchronizing TCS output stores.
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* For example, passes that write an output at the beginning of the shader
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* and load it at the end can use this to determine whether they have to
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* insert a barrier or whether the shader already contains a barrier.
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*/
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bool always_executes_barrier : 1;
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/* Whether outer tess levels <= 0 can be written by the shader. */
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bool can_discard_patches : 1;
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} nir_tcs_info;
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void
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nir_gather_tcs_info(const nir_shader *nir, nir_tcs_info *info,
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enum tess_primitive_mode prim,
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enum gl_tess_spacing spacing);
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#ifdef __cplusplus
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}
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#endif
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#endif /* NIR_TCS_INFO_H */
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