mesa/src/amd
Friedrich Vock 0b251d4362 radv: Add driconf to always drain waves before writing timestamps
UE4's Vulkan backend uses vkCmdWriteTimestamp with TOP_OF_PIPE
to measure how long a workload took in the GPU Benchmark. This is wrong
and writes the timestamp before the workload is actually finished,
making it seem like the GPU is much faster than it actually is.
This caused subsequent benchmark passes to contain way too big workloads,
which caused soft hangs on slower GPUs.

Fixes GPU hangs with Splitgate during automatic settings configuration.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22823>
2023-05-03 15:24:00 +00:00
..
addrlib amd: update addrlib 2023-03-29 20:36:09 +00:00
ci radv/ci: document another vkcts flake on vega10 2023-04-26 08:32:56 +00:00
common ac/nir: fix 8-bit/10-bit PS exports clamping 2023-04-28 17:38:06 +00:00
compiler aco: allow no export instruction for gfx10+ fs 2023-04-28 11:33:28 +08:00
drm-shim amd: fix typos 2023-04-13 23:08:22 +00:00
llvm aco,ac/llvm,radv,radeonsi: handle ps bc optimization in nir for radv 2023-04-26 03:27:26 +00:00
registers amd/registers: use gfx9 packet definitions for gfx940 2023-04-06 15:00:54 +00:00
vulkan radv: Add driconf to always drain waves before writing timestamps 2023-05-03 15:24:00 +00:00
.clang-format amd: Add radv_foreach_stage to ForEachMacros. 2023-03-27 08:29:35 +00:00
meson.build meson: build radeon drm-shim also for r300 and r600 2022-11-16 14:37:47 +00:00