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https://gitlab.freedesktop.org/mesa/mesa.git
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5ac72c5f56
This is not used yet. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33284>
317 lines
7.8 KiB
C
317 lines
7.8 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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* Copyright 2024 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef AC_DESCRIPTORS_H
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#define AC_DESCRIPTORS_H
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#include "ac_gpu_info.h"
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#include "ac_surface.h"
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#include "util/format/u_format.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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unsigned
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ac_map_swizzle(unsigned swizzle);
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struct ac_sampler_state {
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unsigned address_mode_u : 3;
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unsigned address_mode_v : 3;
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unsigned address_mode_w : 3;
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unsigned max_aniso_ratio : 3;
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unsigned depth_compare_func : 3;
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unsigned unnormalized_coords : 1;
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unsigned cube_wrap : 1;
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unsigned trunc_coord : 1;
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unsigned filter_mode : 2;
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unsigned mag_filter : 2;
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unsigned min_filter : 2;
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unsigned mip_filter : 2;
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unsigned aniso_single_level : 1;
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unsigned border_color_type : 2;
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unsigned border_color_ptr : 12;
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float min_lod;
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float max_lod;
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float lod_bias;
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};
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void
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ac_build_sampler_descriptor(const enum amd_gfx_level gfx_level,
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const struct ac_sampler_state *state,
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uint32_t desc[4]);
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struct ac_fmask_state {
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const struct radeon_surf *surf;
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uint64_t va;
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uint32_t width : 16;
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uint32_t height : 16;
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uint32_t depth : 14;
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uint32_t type : 4;
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uint32_t first_layer : 14;
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uint32_t last_layer : 13;
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uint32_t num_samples : 5;
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uint32_t num_storage_samples : 4;
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uint32_t tc_compat_cmask : 1;
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};
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void
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ac_build_fmask_descriptor(const enum amd_gfx_level gfx_level,
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const struct ac_fmask_state *state,
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uint32_t desc[8]);
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struct ac_texture_state {
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struct radeon_surf *surf;
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enum pipe_format format;
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enum pipe_format img_format;
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uint32_t width : 17;
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uint32_t height : 17;
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uint32_t depth : 15;
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uint32_t type : 4;
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enum pipe_swizzle swizzle[4];
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uint32_t num_samples : 5;
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uint32_t num_storage_samples : 5;
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uint32_t first_level : 4;
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uint32_t last_level : 5;
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uint32_t num_levels : 6;
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uint32_t first_layer : 14;
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uint32_t last_layer : 13;
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float min_lod;
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struct {
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uint32_t uav3d : 1;
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uint32_t upgraded_depth : 1;
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} gfx10;
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struct {
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const struct ac_surf_nbc_view *nbc_view;
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} gfx9;
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uint32_t dcc_enabled : 1;
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uint32_t tc_compat_htile_enabled : 1;
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uint32_t aniso_single_level : 1;
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};
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void
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ac_build_texture_descriptor(const struct radeon_info *info,
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const struct ac_texture_state *state,
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uint32_t desc[8]);
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uint32_t
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ac_tile_mode_index(const struct radeon_surf *surf,
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unsigned level,
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bool stencil);
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struct ac_mutable_tex_state {
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const struct radeon_surf *surf;
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uint64_t va;
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struct {
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uint32_t write_compress_enable : 1;
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uint32_t iterate_256 : 1;
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} gfx10;
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struct {
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const struct ac_surf_nbc_view *nbc_view;
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} gfx9;
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struct {
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const struct legacy_surf_level *base_level_info;
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uint32_t base_level;
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uint32_t block_width;
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} gfx6;
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uint32_t is_stencil : 1;
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uint32_t dcc_enabled : 1;
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uint32_t tc_compat_htile_enabled : 1;
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};
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void
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ac_set_mutable_tex_desc_fields(const struct radeon_info *info,
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const struct ac_mutable_tex_state *state,
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uint32_t desc[8]);
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struct ac_buffer_state {
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uint64_t va;
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uint32_t size;
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enum pipe_format format;
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enum pipe_swizzle swizzle[4];
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uint32_t stride;
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uint32_t swizzle_enable : 2;
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uint32_t element_size : 2;
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uint32_t index_stride : 2;
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uint32_t add_tid : 1;
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uint32_t gfx10_oob_select : 2;
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struct {
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uint32_t compression_en : 1;
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uint32_t write_compress_enable : 1;
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} gfx12;
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};
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void
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ac_set_buf_desc_word3(const enum amd_gfx_level gfx_level,
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const struct ac_buffer_state *state,
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uint32_t *rsrc_word3);
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void
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ac_build_buffer_descriptor(const enum amd_gfx_level gfx_level,
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const struct ac_buffer_state *state,
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uint32_t desc[4]);
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void
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ac_build_raw_buffer_descriptor(const enum amd_gfx_level gfx_level,
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uint64_t va,
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uint32_t size,
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uint32_t desc[4]);
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void
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ac_build_attr_ring_descriptor(const enum amd_gfx_level gfx_level,
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uint64_t va,
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uint32_t size,
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uint32_t stride,
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uint32_t desc[4]);
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struct ac_ds_state {
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const struct radeon_surf *surf;
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uint64_t va;
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enum pipe_format format;
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uint32_t width : 17;
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uint32_t height : 17;
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uint32_t level : 5;
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uint32_t num_levels : 6;
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uint32_t num_samples : 5;
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uint32_t first_layer : 14;
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uint32_t last_layer : 14;
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uint32_t allow_expclear : 1;
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uint32_t stencil_only : 1;
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uint32_t z_read_only : 1;
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uint32_t stencil_read_only : 1;
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uint32_t htile_enabled : 1;
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uint32_t htile_stencil_disabled : 1;
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uint32_t vrs_enabled : 1;
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};
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struct ac_ds_surface {
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uint64_t db_depth_base;
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uint64_t db_stencil_base;
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uint32_t db_depth_view;
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uint32_t db_depth_size;
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uint32_t db_z_info;
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uint32_t db_stencil_info;
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union {
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struct {
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uint64_t hiz_base;
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uint32_t hiz_info;
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uint32_t hiz_size_xy;
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uint64_t his_base;
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uint32_t his_info;
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uint32_t his_size_xy;
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uint32_t db_depth_view1;
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} gfx12;
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struct {
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uint64_t db_htile_data_base;
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uint32_t db_depth_info;
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uint32_t db_depth_slice;
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uint32_t db_htile_surface;
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uint32_t db_z_info2;
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uint32_t db_stencil_info2;
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} gfx6;
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} u;
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};
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void
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ac_init_ds_surface(const struct radeon_info *info, const struct ac_ds_state *state, struct ac_ds_surface *ds);
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struct ac_mutable_ds_state {
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const struct ac_ds_surface *ds; /* original DS surface */
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enum pipe_format format;
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uint32_t tc_compat_htile_enabled : 1;
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uint32_t zrange_precision : 1;
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uint32_t no_d16_compression : 1;
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};
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void
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ac_set_mutable_ds_surface_fields(const struct radeon_info *info, const struct ac_mutable_ds_state *state,
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struct ac_ds_surface *ds);
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struct ac_cb_state {
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const struct radeon_surf *surf;
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enum pipe_format format;
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uint32_t width : 17;
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uint32_t height : 17;
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uint32_t first_layer : 14;
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uint32_t last_layer : 14;
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uint32_t num_layers : 14;
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uint32_t num_samples : 5;
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uint32_t num_storage_samples : 5;
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uint32_t base_level : 5;
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uint32_t num_levels : 6;
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struct {
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struct ac_surf_nbc_view *nbc_view;
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} gfx10;
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};
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struct ac_cb_surface {
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uint32_t cb_color_info;
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uint32_t cb_color_view;
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uint32_t cb_color_view2;
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uint32_t cb_color_attrib;
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uint32_t cb_color_attrib2; /* GFX9+ */
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uint32_t cb_color_attrib3; /* GFX10+ */
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uint32_t cb_dcc_control;
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uint64_t cb_color_base;
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uint64_t cb_color_cmask;
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uint64_t cb_color_fmask;
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uint64_t cb_dcc_base;
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uint32_t cb_color_slice;
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uint32_t cb_color_cmask_slice;
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uint32_t cb_color_fmask_slice;
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union {
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uint32_t cb_color_pitch; /* GFX6-GFX8 */
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uint32_t cb_mrt_epitch; /* GFX9+ */
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};
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};
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void
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ac_init_cb_surface(const struct radeon_info *info, const struct ac_cb_state *state, struct ac_cb_surface *cb);
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struct ac_mutable_cb_state {
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const struct radeon_surf *surf;
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const struct ac_cb_surface *cb; /* original CB surface */
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uint64_t va;
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uint32_t base_level : 5;
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uint32_t num_samples : 5;
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uint32_t fmask_enabled : 1;
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uint32_t cmask_enabled : 1;
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uint32_t fast_clear_enabled : 1;
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uint32_t tc_compat_cmask_enabled : 1;
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uint32_t dcc_enabled : 1;
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struct {
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struct ac_surf_nbc_view *nbc_view;
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} gfx10;
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};
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void
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ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
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struct ac_cb_surface *cb);
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#ifdef __cplusplus
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}
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#endif
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#endif
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