Samuel Pitoiset 2eba273314 radv: fix handling divisor == 0 with dynamic vertex input state ... When the divisor is 0, the compiler should generate a different VS prolog instead of re-using a previous prolog that uses nontrivial divisors. This is because divisor == 0 and divisor > 1 should use a different path to guarantee that the index is correctly computed. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16009> (cherry picked from commit f525706e77)		2022-04-27 11:19:10 -07:00
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addrlib	amd: update addrlib	2022-03-01 17:03:00 +00:00
ci	radv/ci: update CI lists against CTS 1.3.1.1	2022-04-05 09:13:41 +02:00
common	ac/surface: fix an addrlib race condition on gfx9	2022-04-24 21:04:52 -07:00
compiler	aco: fix load_barycentric_at_{sample,offset} on GFX6-7	2022-04-26 09:05:08 -07:00
drm-shim	r300/r600: Add drm-shim support.	2022-02-02 00:59:08 +00:00
llvm	ac/llvm: implement load_shared2_amd/store_shared2_amd	2022-04-13 23:08:07 +00:00
registers	amd: remove the _UMD suffix from register definitions	2022-02-22 11:41:04 +00:00
vulkan	radv: fix handling divisor == 0 with dynamic vertex input state	2022-04-27 11:19:10 -07:00
.clang-format	radv: allow holes in inline push constants	2022-04-12 11:44:30 +00:00
meson.build	r300/r600: Add drm-shim support.	2022-02-02 00:59:08 +00:00