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https://gitlab.freedesktop.org/mesa/mesa.git
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130a066d58
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40481>
118 lines
6.1 KiB
C
118 lines
6.1 KiB
C
/* Based on anv:
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* Copyright © 2015 Intel Corporation
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*
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* Copyright © 2016 Red Hat Inc.
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* Copyright © 2018 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_META_NIR_H
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#define RADV_META_NIR_H
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#include "compiler/shader_enums.h"
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#include "vulkan/vulkan_core.h"
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#include "nir_defines.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct radeon_surf;
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enum amd_gfx_level;
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nir_builder PRINTFLIKE(2, 3) radv_meta_nir_init_shader(mesa_shader_stage stage, const char *name, ...);
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nir_shader *radv_meta_nir_build_vs_generate_vertices(void);
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nir_shader *radv_meta_nir_build_fs_noop(void);
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nir_def *radv_meta_nir_get_global_ids(nir_builder *b, unsigned num_components);
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void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
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nir_shader *radv_meta_nir_build_fill_memory_shader(uint32_t bytes_per_invocation);
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nir_shader *radv_meta_nir_build_copy_memory_shader(uint32_t bytes_per_invocation);
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nir_shader *radv_meta_nir_build_blit_vertex_shader(void);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_itob_compute_shader(bool is_3d);
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nir_shader *radv_meta_nir_build_btoi_compute_shader(bool is_3d);
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nir_shader *radv_meta_nir_build_itoi_compute_shader(bool src_3d, bool dst_3d, int samples);
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nir_shader *radv_meta_nir_build_cleari_compute_shader(bool is_3d, int samples);
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nir_shader *radv_meta_nir_build_cleari_96bit_compute_shader(void);
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typedef nir_def *(*radv_meta_nir_texel_fetch_build_func)(nir_builder *, uint32_t, nir_def *, bool, bool);
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nir_def *radv_meta_nir_build_blit2d_texel_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
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bool is_multisampled);
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nir_def *radv_meta_nir_build_blit2d_buffer_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
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bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_vertex_shader(void);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d,
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bool is_multisampled);
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void radv_meta_nir_build_clear_color_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs,
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uint32_t frag_output);
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void radv_meta_nir_build_clear_depthstencil_shaders(struct nir_shader **out_vs, struct nir_shader **out_fs,
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bool unrestricted);
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nir_shader *radv_meta_nir_build_clear_htile_mask_shader(void);
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nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(bool is_msaa);
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nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
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const struct radeon_surf *surf);
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nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(enum amd_gfx_level gfx_level, uint32_t gb_addr_config,
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const struct radeon_surf *surf);
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nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(void);
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nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(void);
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nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(int samples);
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nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(int samples);
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enum radv_meta_resolve_compute_type {
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RADV_META_RESOLVE_COMPUTE_NORM,
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RADV_META_RESOLVE_COMPUTE_NORM_SRGB,
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RADV_META_RESOLVE_COMPUTE_INTEGER,
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RADV_META_RESOLVE_COMPUTE_FLOAT,
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RADV_META_RESOLVE_COMPUTE_COUNT,
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};
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nir_shader *radv_meta_nir_build_resolve_cs(bool use_fmask, enum radv_meta_resolve_compute_type type, int samples,
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VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode);
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nir_shader *radv_meta_nir_build_resolve_fs(bool use_fmask, int samples, bool is_integer, VkImageAspectFlags aspects,
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VkResolveModeFlagBits resolve_mode);
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nir_shader *radv_meta_nir_build_clear_hiz_compute_shader(int samples);
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nir_shader *radv_meta_nir_build_copy_memory_indirect_preprocess_cs(void);
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nir_shader *radv_meta_nir_build_copy_memory_indirect_cs(void);
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nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_preprocess_cs(void);
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nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_cs(uint8_t fmt_block_width, uint8_t fmt_block_height,
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uint8_t fmt_block_depth, uint8_t fmt_element_size_B,
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bool is_3d);
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nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_vs(uint8_t fmt_block_width, uint8_t fmt_block_height,
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uint8_t fmt_block_depth);
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nir_shader *radv_meta_nir_build_copy_memory_to_image_indirect_fs(VkImageAspectFlags aspect_mask,
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uint8_t fmt_block_width, uint8_t fmt_block_height,
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uint8_t fmt_element_size_B);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RADV_META_NIR_H */
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