Samuel Pitoiset 2d18645b1f radv: simplify checking for PS epilogs in radv_pipeline_init_blend_state() ... This is equivalent. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28672>		2024-04-16 07:37:32 +00:00
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addrlib	amd: fix addrlib regression	2024-03-22 08:25:21 +00:00
ci	radv: stop ignoring shader stages that don't need to be imported with GPL	2024-04-12 06:24:43 +00:00
common	ac/nir: add ac_nir_opt_pack_half	2024-04-15 23:34:22 +00:00
compiler	aco: remove occupancy check in dealloc_vgprs()	2024-04-11 18:30:47 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	nir: add nir_intrinsic_optimization_barrier_sgpr_amd	2024-04-13 16:45:08 +00:00
registers	amd/registers: add correct gfx11.x enums for BINNING_MODE	2024-03-11 23:36:55 +00:00
vpelib	radeonsi/vpe: support vpe 1.1	2024-03-25 00:59:02 +00:00
vulkan	radv: simplify checking for PS epilogs in radv_pipeline_init_blend_state()	2024-04-16 07:37:32 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00