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9b5ba06122
MI_REPORT_PERF_COUNT reports all 64 PEC counters, so there is no need to read individual registers. Also the individual registers reads privileged and UMDs can't access it, causing it to always read as always zero and overwritting valid data read with MI_REPORT_PERF_COUNT. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29529>
97 lines
4.2 KiB
C
97 lines
4.2 KiB
C
/*
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* Copyright © 2019 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef INTEL_PERF_REGS_H
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#define INTEL_PERF_REGS_H
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#define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low))
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/* GT core frequency counters */
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#define GFX7_RPSTAT1 0xA01C
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#define GFX7_RPSTAT1_CURR_GT_FREQ_SHIFT 7
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#define GFX7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
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#define GFX7_RPSTAT1_PREV_GT_FREQ_SHIFT 0
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#define GFX7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
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#define GFX9_RPSTAT0 0xA01C
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#define GFX9_RPSTAT0_CURR_GT_FREQ_SHIFT 23
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#define GFX9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
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#define GFX9_RPSTAT0_PREV_GT_FREQ_SHIFT 0
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#define GFX9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
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/* Programmable perf 64bits counters (used for GTRequestQueueFull counter on
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* gfx7-11)
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*/
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#define PERF_CNT_1_DW0 0x91b8
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#define PERF_CNT_2_DW0 0x91c0
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#define PERF_CNT_VALUE_MASK ((1ull << 44) - 1)
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/* Global OA perf counters */
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#define GFX7_N_OA_PERF_A32 44
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#define GFX7_OA_PERF_A32(idx) (0x2800 + (idx) * 4)
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#define GFX8_OA_PERF_TICKS 0x2910
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#define GFX8_N_OA_PERF_A64 32
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#define GFX8_N_OA_PERF_A32 4
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#define GFX8_N_OA_PERF_B32 8
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#define GFX8_N_OA_PERF_C32 8
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#define GFX8_OA_PERF_A64_LDW(idx) (0x2800 + (idx) * 8)
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#define GFX8_OA_PERF_A64_UDW(idx) (0x2800 + (idx) * 8 + 4)
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#define GFX8_OA_PERF_A32(idx) (0x2900 + (idx) * 4)
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#define GFX8_OA_PERF_B32(idx) (0x2920 + (idx) * 4)
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#define GFX8_OA_PERF_C32(idx) (0x2940 + (idx) * 4)
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#define GFX12_OAG_PERF_TICKS 0xda90
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#define GFX12_N_OAG_PERF_A64 32
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#define GFX12_N_OAG_PERF_A32 4
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#define GFX12_N_OAG_PERF_B32 8
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#define GFX12_N_OAG_PERF_C32 8
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#define GFX12_OAG_PERF_A64_LDW(idx) (0xd980 + (idx) * 8)
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#define GFX12_OAG_PERF_A64_UDW(idx) (0xd980 + (idx) * 8 + 4)
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#define GFX12_OAG_PERF_A32(idx) (0xda80 + (idx) * 4)
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#define GFX12_OAG_PERF_B32(idx) (0xda94 + (idx) * 4)
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#define GFX12_OAG_PERF_C32(idx) (0xdab4 + (idx) * 4)
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#define GFX125_OAG_PERF_A36 (0xdb20)
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#define GFX125_OAG_PERF_A37 (0xdb28)
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/* Pipeline statistic counters */
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#define IA_VERTICES_COUNT 0x2310
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#define IA_PRIMITIVES_COUNT 0x2318
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#define VS_INVOCATION_COUNT 0x2320
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#define HS_INVOCATION_COUNT 0x2300
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#define DS_INVOCATION_COUNT 0x2308
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#define GS_INVOCATION_COUNT 0x2328
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#define GS_PRIMITIVES_COUNT 0x2330
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#define CL_INVOCATION_COUNT 0x2338
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#define CL_PRIMITIVES_COUNT 0x2340
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#define PS_INVOCATION_COUNT 0x2348
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#define CS_INVOCATION_COUNT 0x2290
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#define PS_DEPTH_COUNT 0x2350
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/* Stream-out counters */
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#define GFX6_SO_PRIM_STORAGE_NEEDED 0x2280
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#define GFX7_SO_PRIM_STORAGE_NEEDED(n) (0x5240 + (n) * 8)
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#define GFX6_SO_NUM_PRIMS_WRITTEN 0x2288
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#define GFX7_SO_NUM_PRIMS_WRITTEN(n) (0x5200 + (n) * 8)
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#endif /* INTEL_PERF_REGS_H */
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