Rhys Perry ec892c4d2b aco: don't reuse misaligned attribute destination VGPRs in VS prologs ... Since we split misaligned attributes, we could overwrite one of these VGPRs in the middle of loading the attribute. For example: v_add_u32_e32 v4, vcc, s7, v1 s_waitcnt lgkmcnt(0) buffer_load_dword v4, v4, s[32:35], 0 idxen buffer_load_dword v5, v4, s[32:35], 0 idxen offset:4 can overwrite the vertex index in the load of the first component. Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>		2024-03-14 15:30:12 +00:00
..
addrlib	amd: update addrlib	2024-03-09 16:56:56 +00:00
ci	radv/ci: Update xfiles based on nightly run	2024-03-14 13:53:45 +00:00
common	ac: use the gfx11 shadowed register tables for gfx11.5	2024-03-11 23:36:55 +00:00
compiler	aco: don't reuse misaligned attribute destination VGPRs in VS prologs	2024-03-14 15:30:12 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	ac/llvm: fix SSBO bounds checking by using raw instead of struct opcodes	2024-03-12 23:00:00 +00:00
registers	amd/registers: add correct gfx11.x enums for BINNING_MODE	2024-03-11 23:36:55 +00:00
vpelib	amd/vpelib: Add UID for 3d Lut and control logic	2024-02-06 14:55:02 +00:00
vulkan	radv,aco: allow VS prologs to increase VGPR usage	2024-03-14 15:30:12 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00