Tim Rowley 2966d9c691 swr: [rasterizer core] align Macrotile FIFO memory to SIMD size ... Align and use streaming store instructions for BE fifo queues. Provides slightly faster enqueue and doesn't pollute the caches. Add appropriate memory fences to ensure streaming writes are globally visible. Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>		2016-10-11 11:22:04 -05:00
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amd	radv: automake: move libamdgpu_addrlib.la to VULKAN_LIB_DEPS	2016-10-11 13:51:09 +01:00
compiler	glsl: Add missing cache_destroy stub function.	2016-10-10 11:17:31 -07:00
egl	egl: add eglSwapBuffersWithDamageKHR	2016-10-11 14:04:26 +01:00
gallium	swr: [rasterizer core] align Macrotile FIFO memory to SIMD size	2016-10-11 11:22:04 -05:00
gbm	gbm: return appropriate error when queryImage() fails	2016-09-27 13:37:21 +01:00
getopt	Introduce .editorconfig	2016-08-31 17:06:54 -07:00
glx	loader/dri3: add get_dri_screen() to the vtable	2016-10-07 11:11:44 +03:00
gtest	Introduce .editorconfig	2016-08-31 17:06:54 -07:00
hgl	glapi/hgl: remove the final user of _glapi_check_table()	2016-10-06 15:03:46 +01:00
intel	intel/genxml: fix building rules for aubinator required headers	2016-10-11 13:53:19 +01:00
loader	loader/dri3: import prime buffers in the currently-bound screen	2016-10-07 11:11:55 +03:00
mapi	glapi: add entry points for GL_ARB_compute_variable_group_size	2016-10-07 00:18:57 +02:00
mesa	mesa: fix error handling in _mesa_TransformFeedbackVaryings	2016-10-11 07:44:33 +03:00
util	util: remove unused variable	2016-10-07 21:24:50 +11:00
Makefile.am	radv: add initial non-conformant radv vulkan driver	2016-10-07 09:16:09 +10:00
SConscript	scons: put the generated git_sha1.h file in top-level src/ directory	2016-06-17 10:33:00 -06:00