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294644643e
Dishonered 2 or DXVK is creating pipelines with empty fragment shaders. With alpha-to-coverage a dynamic state, we currently consider there is a need for a render target but if the shader is not writing anything, it's not needed. This change only considers the color output writes as it's the alpha channel there that is used for coverage computation. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Ivan Briano <ivan.briano@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41711>
449 lines
16 KiB
C
449 lines
16 KiB
C
/*
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* Copyright © 2015 Intel Corporation
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* SPDX-License-Identifier: MIT
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*/
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#pragma once
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#include "brw_reg.h"
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#include "compiler/nir/nir.h"
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#include "brw_compiler.h"
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#include "nir_builder.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define BRW_TEX_INSTR_FUSED_EU_DISABLE (1u << 30)
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extern const struct nir_shader_compiler_options brw_scalar_nir_options;
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struct brw_pass_tracker;
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void
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brw_fill_tess_info_from_shader_info(struct brw_tess_info *brw_info,
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const shader_info *shader_info);
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int type_size_vec4(const struct glsl_type *type, bool bindless);
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int type_size_dvec4(const struct glsl_type *type, bool bindless);
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struct brw_mem_access_cb_data {
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const struct intel_device_info *devinfo;
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};
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static inline int
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type_size_scalar_bytes(const struct glsl_type *type, bool bindless)
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{
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return glsl_count_dword_slots(type, bindless) * 4;
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}
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static inline int
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type_size_vec4_bytes(const struct glsl_type *type, bool bindless)
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{
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return type_size_vec4(type, bindless) * 16;
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}
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struct brw_nir_compiler_opts {
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/* Soft floating point implementation shader */
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const nir_shader *softfp64;
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/* Whether robust image access is enabled */
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bool robust_image_access;
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/* Input vertices for TCS stage (0 means dynamic) */
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unsigned input_vertices;
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};
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/* UBO surface index can come in 2 flavors :
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* - nir_intrinsic_resource_intel
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* - anything else
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*
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* In the first case, checking that the surface index is const requires
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* checking resource_intel::src[1]. In any other case it's a simple
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* nir_src_is_const().
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*
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* This function should only be called on src[0] of load_ubo intrinsics.
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*/
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static inline bool
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brw_nir_ubo_surface_index_is_pushable(nir_src src)
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{
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nir_intrinsic_instr *intrin = nir_src_as_intrinsic(src);
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if (intrin && intrin->intrinsic == nir_intrinsic_resource_intel) {
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return (nir_intrinsic_resource_access_intel(intrin) &
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nir_resource_intel_pushable);
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}
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return nir_src_is_const(src);
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}
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/* This helper return the binding table index of a surface access (any
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* buffer/image/etc...). It works off the source of one of the intrinsics
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* (load_ubo, load_ssbo, store_ssbo, load_image, store_image, etc...).
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*
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* If the source is constant, then this is the binding table index. If we're
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* going through a resource_intel intel intrinsic, then we need to check
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* src[1] of that intrinsic.
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*/
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static inline unsigned
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brw_nir_ubo_surface_index_get_bti(nir_src src)
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{
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if (nir_src_is_const(src))
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return nir_src_as_uint(src);
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assert(nir_src_is_intrinsic(src));
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nir_intrinsic_instr *intrin = nir_def_as_intrinsic(src.ssa);
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if (!intrin || intrin->intrinsic != nir_intrinsic_resource_intel)
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return UINT32_MAX;
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/* In practice we could even drop this intrinsic because the bindless
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* access always operate from a base offset coming from a push constant, so
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* they can never be constant.
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*/
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if (nir_intrinsic_resource_access_intel(intrin) &
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nir_resource_intel_bindless)
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return UINT32_MAX;
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if (!nir_src_is_const(intrin->src[1]))
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return UINT32_MAX;
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return nir_src_as_uint(intrin->src[1]);
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}
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/* Returns true if a fragment shader needs at least one render target */
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static inline bool
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brw_nir_fs_needs_null_rt(const struct intel_device_info *devinfo,
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nir_shader *nir, bool alpha_to_coverage)
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{
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assert(nir->info.stage == MESA_SHADER_FRAGMENT);
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/* Null-RT bit in the render target write extended descriptor is only
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* available on Gfx11+.
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*/
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if (devinfo->ver < 11)
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return true;
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/* Depth/Stencil needs a valid render target even if there is no color
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* output.
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*/
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if (nir->info.outputs_written & (BITFIELD_BIT(FRAG_RESULT_DEPTH) |
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BITFIELD_BIT(FRAG_RESULT_STENCIL) |
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BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)))
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return true;
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return alpha_to_coverage &&
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(nir->info.outputs_written &
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BITFIELD_RANGE(FRAG_RESULT_DATA0, 8)) != 0;
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}
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void brw_preprocess_nir(const struct brw_compiler *compiler,
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nir_shader *nir,
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const struct brw_nir_compiler_opts *opts);
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bool
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brw_nir_fence_shared_stores(nir_shader *shader);
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void
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brw_nir_link_shaders(const struct brw_compiler *compiler,
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nir_shader *producer, nir_shader *consumer);
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bool brw_nir_lower_cs_intrinsics(nir_shader *nir,
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const struct intel_device_info *devinfo,
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struct brw_cs_prog_data *prog_data);
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bool brw_nir_lower_cs_subgroup_id(nir_shader *nir,
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const struct intel_device_info *devinfo,
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unsigned subgroup_id_offset);
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bool brw_nir_lower_alpha_to_coverage(nir_shader *shader);
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bool brw_needs_vertex_attributes_bypass(const nir_shader *shader);
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void brw_nir_lower_fs_barycentrics(nir_shader *shader);
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bool brw_nir_lower_fully_covered(nir_shader *nir);
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struct brw_lower_urb_cb_data {
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const struct intel_device_info *devinfo;
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/** Maximum amount of pushed data in bytes */
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unsigned max_push_bytes;
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/* If true, all access is guaranteed to be vec4 (128-bit) aligned.
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* offset and base are in units of 128-bit vec4 slots.
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*
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* If false, all access is guaranteed to be 32-bit aligned.
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* offset is in 32-bit units, but base is still in 128-bit vec4 units,
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*/
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bool vec4_access;
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/** Map from VARYING_SLOT_* to a vec4 slot index */
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const int8_t *varying_to_slot;
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/** Stride in bytes between each vertex's worth of per-vertex varyings */
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unsigned per_vertex_stride;
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/** Do we need to use dynamic TES input bases (intel_nir_tess_field)? */
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bool dynamic_tes;
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/** Static offsets and sizes (in slots) for TES inputs */
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int tes_builtins_slot_offset;
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int tes_per_patch_slots;
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/* Offset in bytes to the start of the per-vertex section */
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uint32_t per_vertex_offset;
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/* Offset in bytes to the start of the per-primitive section */
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uint32_t per_primitive_offset;
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/* Stride in bytes between successive primitives */
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uint32_t per_primitive_stride;
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/** Stride in bytes between PrimitiveIndices[] array elements */
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uint32_t per_primitive_indices_stride;
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/**
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* Map from VARYING_SLOT_* to the offset in bytes within the
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* per-primitive section of the MUE.
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*/
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const int *per_primitive_byte_offsets;
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};
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bool brw_nir_lower_inputs_to_urb_intrinsics(nir_shader *, const struct brw_lower_urb_cb_data *);
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bool brw_nir_lower_outputs_to_urb_intrinsics(nir_shader *, const struct brw_lower_urb_cb_data *);
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bool brw_nir_lower_deferred_urb_writes(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct intel_vue_map *vue_map,
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unsigned extra_urb_slot_offset,
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unsigned gs_vertex_stride);
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void brw_nir_opt_vectorize_urb(struct brw_pass_tracker *pt);
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void brw_nir_lower_vs_inputs(nir_shader *nir);
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void brw_nir_lower_gs_inputs(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct intel_vue_map *vue_map,
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unsigned *out_urb_read_length);
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void brw_nir_lower_tes_inputs(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct intel_vue_map *vue);
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void brw_nir_lower_fs_inputs(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct brw_fs_prog_key *key);
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void brw_nir_lower_vue_outputs(nir_shader *nir);
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void brw_nir_lower_tcs_inputs(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct intel_vue_map *vue);
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void brw_nir_lower_tcs_outputs(nir_shader *nir,
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const struct intel_device_info *devinfo,
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const struct intel_vue_map *vue,
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enum tess_primitive_mode tes_primitive_mode);
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void brw_nir_lower_mesh_outputs(nir_shader *nir,
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const struct brw_mue_map *map);
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void brw_nir_lower_fs_outputs(nir_shader *nir);
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bool brw_nir_lower_fs_load_output(nir_shader *shader,
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const struct brw_fs_prog_key *key);
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bool brw_nir_lower_fs_config_intel(nir_shader *nir,
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const struct brw_fs_prog_key *key,
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const struct brw_fs_prog_data *prog_data);
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bool brw_nir_lower_frag_coord_z(nir_shader *nir,
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const struct intel_device_info *devinfo);
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bool brw_nir_lower_cmat(nir_shader *nir, unsigned subgroup_size);
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struct brw_nir_lower_storage_image_opts {
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bool lower_loads;
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bool lower_stores;
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bool lower_stores_64bit;
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bool lower_loads_without_formats;
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};
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bool brw_nir_lower_storage_image(nir_shader *nir,
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const struct brw_compiler *compiler,
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const struct brw_nir_lower_storage_image_opts *opts);
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bool brw_nir_lower_texel_address(nir_shader *shader,
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const struct intel_device_info *devinfo,
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enum isl_tiling tiling);
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bool brw_nir_lower_mcs_fetch(nir_shader *shader,
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const struct intel_device_info *devinfo);
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bool brw_nir_texture_backend_opcode(nir_shader *shader,
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const struct intel_device_info *devinfo);
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bool brw_nir_pre_lower_texture(nir_shader *nir,
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const struct intel_device_info *devinfo);
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bool brw_nir_lower_texture(nir_shader *nir);
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bool brw_nir_lower_sample_index_in_coord(nir_shader *nir);
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bool brw_nir_lower_immediate_offsets(nir_shader *shader);
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bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
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const struct
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intel_device_info *devinfo);
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bool brw_nir_lower_simd(nir_shader *nir);
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void brw_postprocess_nir_opts(struct brw_pass_tracker *pt);
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void brw_postprocess_nir_out_of_ssa(struct brw_pass_tracker *pt,
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bool debug_enabled);
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static inline void
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brw_postprocess_nir(struct brw_pass_tracker *pt,
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bool debug_enabled)
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{
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brw_postprocess_nir_opts(pt);
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brw_postprocess_nir_out_of_ssa(pt, debug_enabled);
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}
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bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
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const uint8_t *attrib_wa_flags);
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bool brw_nir_apply_trig_workarounds(nir_shader *nir);
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bool brw_nir_limit_trig_input_range_workaround(nir_shader *nir);
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bool brw_nir_apply_sqrt_workarounds(nir_shader *nir);
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bool brw_nir_lower_fsign(nir_shader *nir);
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bool brw_nir_opt_fsat(nir_shader *);
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void brw_nir_apply_key(struct brw_pass_tracker *pt,
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const struct brw_base_prog_key *key,
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unsigned max_subgroup_size);
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unsigned brw_nir_api_subgroup_size(const nir_shader *nir,
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unsigned hw_subgroup_size);
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enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
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enum lsc_opcode lsc_op_for_nir_intrinsic(const nir_intrinsic_instr *intrin);
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enum brw_reg_type brw_type_for_base_type(enum glsl_base_type base_type);
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enum brw_reg_type brw_type_for_nir_type(const struct intel_device_info *devinfo,
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nir_alu_type type);
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struct brw_nir_vectorize_mem_cb_data {
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const struct intel_device_info *devinfo;
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};
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bool brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
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unsigned bit_size,
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unsigned num_components,
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int64_t hole_size,
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nir_intrinsic_instr *low,
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nir_intrinsic_instr *high,
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void *data);
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/**
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* Gets the size of a nir_load_*_uniform_block_intel after its lowered
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* by the backend to a block load message, note that page faults can
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* happen if this is not accounted for when using these intrinsics.
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*/
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static inline unsigned
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brw_uniform_block_size(const struct intel_device_info *devinfo,
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unsigned num_components)
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{
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/* Round up to a supported block size, or to the nearest multiple of
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* 16 components if its any larger.
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*/
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return num_components > 8 ? align(num_components, 16)
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: num_components > 4 ? 8
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: !devinfo->has_lsc ? 4
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: num_components;
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}
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void brw_nir_optimize(struct brw_pass_tracker *pt);
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bool brw_nir_move_interpolation_to_top(nir_shader *nir);
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nir_def *brw_nir_load_global_const(nir_builder *b,
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nir_intrinsic_instr *load_uniform,
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nir_def *base_addr,
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unsigned off);
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void brw_nir_quick_pressure_estimate(nir_shader *nir,
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const struct intel_device_info *devinfo,
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unsigned simd_est[3]);
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const struct glsl_type *brw_nir_get_var_type(const struct nir_shader *nir,
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nir_variable *var);
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static inline nir_variable_mode
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brw_nir_no_indirect_mask(mesa_shader_stage stage)
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{
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nir_variable_mode indirect_mask = (nir_variable_mode) 0;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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case MESA_SHADER_FRAGMENT:
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indirect_mask |= nir_var_shader_in;
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break;
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default:
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/* Everything else can handle indirect inputs */
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break;
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}
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if (stage != MESA_SHADER_TESS_CTRL &&
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stage != MESA_SHADER_TASK &&
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stage != MESA_SHADER_MESH)
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indirect_mask |= nir_var_shader_out;
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return indirect_mask;
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}
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nir_variable *
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brw_nir_find_complete_variable_with_location(nir_shader *shader,
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nir_variable_mode mode,
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int location);
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nir_def *
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brw_nir_vertex_attribute_offset(nir_builder *b,
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nir_def *attr_idx,
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const struct intel_device_info *devinfo);
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static inline bool
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brw_nir_mesh_shader_needs_wa_18019110168(const struct intel_device_info *devinfo,
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nir_shader *shader)
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{
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return intel_needs_workaround(devinfo, 18019110168) &&
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(shader->info.outputs_written & (VARYING_BIT_CLIP_DIST0 |
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VARYING_BIT_CLIP_DIST1)) &&
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(shader->info.per_primitive_outputs & ~(VARYING_BIT_PRIMITIVE_INDICES |
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VARYING_BIT_PRIMITIVE_COUNT));
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}
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static inline bool
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brw_nir_fragment_shader_needs_wa_18019110168(const struct intel_device_info *devinfo,
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enum intel_sometimes mesh_input,
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nir_shader *shader)
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{
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return intel_needs_workaround(devinfo, 18019110168) &&
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mesh_input != INTEL_NEVER &&
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(shader->info.per_primitive_inputs != 0 ||
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(shader->info.inputs_read & VARYING_BIT_PRIMITIVE_ID));
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}
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void
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brw_nir_mesh_convert_attrs_prim_to_vert(struct nir_shader *nir,
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struct brw_compile_mesh_params *params,
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int *wa_mapping);
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bool
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brw_nir_frag_convert_attrs_prim_to_vert(struct nir_shader *nir,
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const int *wa_mapping);
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bool
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brw_nir_frag_convert_attrs_prim_to_vert_indirect(struct nir_shader *nir,
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const struct intel_device_info *devinfo,
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struct brw_compile_fs_params *params);
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unsigned
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brw_nir_pack_vs_input(nir_shader *nir, struct brw_vs_prog_data *prog_data);
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bool brw_nir_opt_divergent_atomics(nir_shader *shader, enum brw_divergent_atomics_flags flags);
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#ifdef __cplusplus
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}
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#endif
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