mesa/src/panfrost/midgard
Alyssa Rosenzweig 261d48fc9b pan/mdg: Refuse to schedule CSEL.vector to SMUL
Even if we only mask a single component from the result of CSEL.vector,
in our IR we treat its semantics as vector which causes trouble with
when scheduled to a scalar unit.

The problematic bundle looks like this:

   vmul.MOV.i32 R31, TMP0.xxxx, R0.yzww
   sadd.MAX.i32 TMP0.y, R0.y, #65408
   smul.CSEL.vector.i32 R0.y, TMP0.y, #127

As the comment in midgard.h illuminates, these CSEL instructions are
actually operating per-bit, lining up with the all-1's booleans in
Midgard. The Bifrost analogue is MUX.i32.bit, not CSEL.i32. We should
probably rename the Midgard instruction to make that clear.

Anyhoo, on the scalar unit, CSEL/MUX operates on the bottom 32-bits of
its source. That's ok for the usual r31.w case, because that's secretly
replicating to its nonexistent register, I think? But that doesn't work
with the CSEL.vector (MUX.vector) form, because the condition it's
actually muxing on is r31.x, which here is R0.y, not the intended R0.x.

Rather than adding more special cases to the already overcomplicated
scheduler (for the dubious benefit of avoiding a small shaderdb
regression), just avoid scheduling CSEL.vector to smul.

With the next patch, fixes:

dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>
2022-12-01 00:52:53 +00:00
..
compiler.h pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled 2022-05-10 13:16:50 +00:00
disassemble.c pan/mdg: Disassemble the .a32 bit 2022-11-02 16:52:11 +00:00
disassemble.h pan/mdg: Remove disassembler stats 2022-08-17 17:25:56 +00:00
helpers.h pan/mdg: Print outmods when printing IR 2022-06-01 14:24:10 -04:00
meson.build meson: remove source_root() call in nir compiler path 2022-08-12 13:11:03 +00:00
midgard.h pan/mdg: Fix out-of-order execution 2022-11-23 20:23:50 +00:00
midgard_address.c pan/mdg: Fix 64-bit address arithmetic 2022-10-27 20:13:11 +00:00
midgard_compile.c tree-wide: Use __func__ instead of __FUNCTION__ in non-gallium code 2022-11-22 06:53:46 +00:00
midgard_compile.h glsl: Drop borrow/carry lowerings in favor of nir 2022-11-15 21:51:04 +00:00
midgard_derivatives.c pan/mdg: improve tex opcode decoding and add missing ops 2021-04-27 07:04:08 +00:00
midgard_emit.c pan/mdg: Fix out-of-order execution 2022-11-23 20:23:50 +00:00
midgard_errata_lod.c nir: adjust nir_src_copy signature to take a nir_instr * 2022-08-30 18:21:44 +00:00
midgard_helper_invocations.c
midgard_liveness.c pan/mdg: Add missing Collabora copyright notices 2020-11-09 16:45:25 +00:00
midgard_nir.h pan/mdg: Lower stores from helpers 2021-02-12 16:44:30 -05:00
midgard_nir_algebraic.py nir,panfrost: Suffix fsat_signed and fclamp_pos with _mali 2021-06-21 09:03:34 -05:00
midgard_nir_lower_helper_writes.c pan/mdg: Lower stores from helpers 2021-02-12 16:44:30 -05:00
midgard_nir_lower_image_bitsize.c pan/mdg: create nir pass to lower image coord bitsize 2021-01-27 12:39:41 +00:00
midgard_ops.c pan/mdg: Refuse to schedule CSEL.vector to SMUL 2022-12-01 00:52:53 +00:00
midgard_ops.h pan/mdg: Remove unused midgard_int_alu_op_prefix 2021-05-18 19:19:01 +00:00
midgard_opt_copy_prop.c pan/mdg: Remove midgard_opt_copy_prop_reg 2021-05-06 16:40:50 +00:00
midgard_opt_dce.c pan/midg: Support 8/16 bit load/store 2022-02-04 17:12:35 -05:00
midgard_opt_perspective.c pan/mdg: properly encode/decode ldst instructions 2021-04-27 07:04:08 +00:00
midgard_print.c pan/mdg: Print 3 sources for CSEL 2022-08-31 14:07:53 +00:00
midgard_print_constant.c pan/mdg: Print outmods when printing IR 2022-06-01 14:24:10 -04:00
midgard_quirks.h panfrost: Don't pass quirks to pan_lower_framebuffer 2022-01-28 17:47:46 +00:00
midgard_ra.c pan/mdg: Fix 16-bit alignment with spiller 2022-10-17 19:11:10 +00:00
midgard_ra_pipeline.c
midgard_schedule.c pan/mdg: Don't pair ST_VARY.a32 with other instrs 2022-11-02 16:52:11 +00:00
mir.c pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled 2022-05-10 13:16:50 +00:00
mir_promote_uniforms.c pan/mdg: Create a mask of UBOs that need to be uploaded 2021-07-03 13:23:29 +00:00
mir_squeeze.c util/hash_table: do not leak u64 struct key 2021-04-29 12:58:23 +02:00
nir_fuse_io_16.c nir: Make nir_ssa_def_rewrite_uses_after take an SSA value 2021-03-08 16:59:55 +00:00