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a821dfbda5
This is meant to remove any integrated GPU only code paths that can't be compiled in CPU architectures different than x86. Discrete GPUS don't have need_clflush set to true so it was just matter of remove some code blocks around need_clflush but was left a check in anv_physical_device_init_heaps() to fail physical device initialization if it ever became false. Signed-off-by: Philippe Lecluse <philippe.lecluse@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19812>
73 lines
2.4 KiB
C
73 lines
2.4 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef INTEL_CLFLUSH_H
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#define INTEL_CLFLUSH_H
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#define CACHELINE_SIZE 64
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#define CACHELINE_MASK 63
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#ifdef SUPPORT_INTEL_INTEGRATED_GPUS
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static inline void
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intel_clflush_range(void *start, size_t size)
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{
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void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK);
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void *end = start + size;
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while (p < end) {
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__builtin_ia32_clflush(p);
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p += CACHELINE_SIZE;
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}
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}
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static inline void
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intel_flush_range(void *start, size_t size)
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{
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__builtin_ia32_mfence();
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intel_clflush_range(start, size);
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}
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static inline void
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intel_invalidate_range(void *start, size_t size)
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{
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if (size == 0)
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return;
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intel_clflush_range(start, size);
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/* Modern Atom CPUs (Baytrail+) have issues with clflush serialization,
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* where mfence is not a sufficient synchronization barrier. We must
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* double clflush the last cacheline. This guarantees it will be ordered
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* after the preceding clflushes, and then the mfence guards against
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* prefetches crossing the clflush boundary.
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*
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* See kernel commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e
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* ("drm: Restore double clflush on the last partial cacheline")
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* and https://bugs.freedesktop.org/show_bug.cgi?id=92845.
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*/
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__builtin_ia32_clflush(start + size - 1);
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__builtin_ia32_mfence();
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}
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#endif /* SUPPORT_INTEL_INTEGRATED_GPUS */
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#endif
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