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534d145e5e
In GLSL-to-NIR we were just setting the base index to 0 whenever there was an indirect so having it expressed as a sum makes no sense. Also, while a base offset may make sense for the memory location (first element in the array, etc.) it makes less sense for the actual uniform buffer index. This may change later, but it seems to make more sense for now. Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
140 lines
5.3 KiB
C
140 lines
5.3 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Connor Abbott (cwabbott0@gmail.com)
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*
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*/
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/**
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* This header file defines all the available intrinsics in one place. It
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* expands to a list of macros of the form:
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*
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* INTRINSIC(name, num_srcs, src_components, has_dest, dest_components,
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* num_variables, num_indices, flags)
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*
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* Which should correspond one-to-one with the nir_intrinsic_info structure. It
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* is included in both ir.h to create the nir_intrinsic enum (with members of
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* the form nir_intrinsic_(name)) and and in opcodes.c to create
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* nir_intrinsic_infos, which is a const array of nir_intrinsic_info structures
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* for each intrinsic.
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*/
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#define ARR(...) { __VA_ARGS__ }
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INTRINSIC(load_var, 0, ARR(), true, 0, 1, 0, NIR_INTRINSIC_CAN_ELIMINATE)
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INTRINSIC(store_var, 1, ARR(0), false, 0, 1, 0, 0)
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INTRINSIC(copy_var, 0, ARR(), false, 0, 2, 0, 0)
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/*
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* Interpolation of input. The interp_var_at* intrinsics are similar to the
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* load_var intrinsic acting an a shader input except that they interpolate
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* the input differently. The at_sample and at_offset intrinsics take an
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* aditional source that is a integer sample id or a vec2 position offset
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* respectively.
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*/
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INTRINSIC(interp_var_at_centroid, 0, ARR(0), true, 0, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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INTRINSIC(interp_var_at_sample, 1, ARR(1), true, 0, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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INTRINSIC(interp_var_at_offset, 1, ARR(2), true, 0, 1, 0,
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NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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/*
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* a barrier is an intrinsic with no inputs/outputs but which can't be moved
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* around/optimized in general
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*/
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#define BARRIER(name) INTRINSIC(name, 0, ARR(), false, 0, 0, 0, 0)
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BARRIER(discard)
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INTRINSIC(emit_vertex, 0, ARR(), false, 0, 0, 1, 0)
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INTRINSIC(end_primitive, 0, ARR(), false, 0, 0, 1, 0)
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/*
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* Atomic counters
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*
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* The *_var variants take an atomic_uint nir_variable, while the other,
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* lowered, variants take a constant buffer index and register offset.
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*/
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#define ATOMIC(name, flags) \
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INTRINSIC(atomic_counter_##name##_var, 0, ARR(), true, 1, 1, 0, flags) \
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INTRINSIC(atomic_counter_##name, 1, ARR(1), true, 1, 0, 1, flags)
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ATOMIC(inc, 0)
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ATOMIC(dec, 0)
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ATOMIC(read, NIR_INTRINSIC_CAN_ELIMINATE)
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#define SYSTEM_VALUE(name, components) \
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INTRINSIC(load_##name, 0, ARR(), true, components, 0, 0, \
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NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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SYSTEM_VALUE(front_face, 1)
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SYSTEM_VALUE(vertex_id, 1)
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SYSTEM_VALUE(instance_id, 1)
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SYSTEM_VALUE(sample_id, 1)
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SYSTEM_VALUE(sample_pos, 2)
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SYSTEM_VALUE(sample_mask_in, 1)
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SYSTEM_VALUE(invocation_id, 1)
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/*
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* The first index is the address to load from, and the second index is the
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* number of array elements to load. Indirect loads have an additional
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* register input, which is added to the constant address to compute the
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* final address to load from. For UBO's (and SSBO's), the first source is
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* the (possibly constant) UBO buffer index and the indirect (if it exists)
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* is the second source.
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*
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* For vector backends, the address is in terms of one vec4, and so each array
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* element is +4 scalar components from the previous array element. For scalar
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* backends, the address is in terms of a single 4-byte float/int and arrays
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* elements begin immediately after the previous array element.
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*/
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#define LOAD(name, extra_srcs, flags) \
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INTRINSIC(load_##name, extra_srcs, ARR(1), true, 0, 0, 2, flags) \
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INTRINSIC(load_##name##_indirect, extra_srcs + 1, ARR(1, 1), \
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true, 0, 0, 2, flags)
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LOAD(uniform, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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LOAD(ubo, 1, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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LOAD(input, 0, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
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/* LOAD(ssbo, 1, 0) */
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/*
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* Stores work the same way as loads, except now the first register input is
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* the value or array to store and the optional second input is the indirect
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* offset.
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*/
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#define STORE(name, num_indices, flags) \
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INTRINSIC(store_##name, 1, ARR(0), false, 0, 0, num_indices, flags) \
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INTRINSIC(store_##name##_indirect, 2, ARR(0, 1), false, 0, 0, \
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num_indices, flags) \
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STORE(output, 2, 0)
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/* STORE(ssbo, 3, 0) */
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LAST_INTRINSIC(store_output_indirect)
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