Marek Olšák 20b9b5d7f5 radeonsi: add struct si_shader_config ... There will be 1 config per variant, which will be a union of configs from {prolog, main, epilog}. For now, just add the structure. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>		2016-01-07 18:26:06 +01:00
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ddebug	gallium/ddebug: regularly log the total number of draw calls	2015-12-12 15:23:50 -05:00
freedreno	gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H support	2016-01-03 16:20:41 -05:00
i915	draw: nuke the interp parameter from vertex_info	2016-01-07 01:58:05 +01:00
ilo	gallium/drivers/ilo: Use unsigned for loop index	2016-01-06 08:04:03 -07:00
llvmpipe	llvmpipe: use ints not unsigned for slots	2016-01-07 01:59:17 +01:00
noop	gallium/drivers: Sanitize NULL checks into canonical form	2015-12-06 17:10:23 +01:00
nouveau	draw: nuke the interp parameter from vertex_info	2016-01-07 01:58:05 +01:00
r300	draw: nuke the interp parameter from vertex_info	2016-01-07 01:58:05 +01:00
r600	gallium/r600: Replace ALIGN_DIVUP with DIV_ROUND_UP	2016-01-06 16:09:12 -05:00
radeon	gallium/radeon: dump LLVM module outside of radeon_llvm_compile	2016-01-03 22:41:16 +01:00
radeonsi	radeonsi: add struct si_shader_config	2016-01-07 18:26:06 +01:00
rbug	gallium/drivers: Trivial code-style cleanup	2015-12-06 17:10:22 +01:00
softpipe	softpipe: tell draw about the vertex layout we want	2016-01-07 02:00:04 +01:00
svga	draw: nuke the interp parameter from vertex_info	2016-01-07 01:58:05 +01:00
trace	gallium/drivers: Trivial code-style cleanup	2015-12-06 17:10:22 +01:00
vc4	vc4: Fix driver build from last minute rebase fix.	2016-01-06 12:49:45 -08:00
virgl	gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H support	2016-01-03 16:20:41 -05:00