Jason Ekstrand 1f7e11a190 genxml: Drop bit 27 from RENDER_SURFACE_STATE::Surface Format ... Bit 27 is the "ASTC Format" bit in the PRMs but we just extended the Surface Format field by one bit and made sure all the ASTC formats have that bit set. Since Gfx12.5 doesn't support ASTC, we can drop that bit from the field and this will cause GenXML packing functions to assert if it's ever set. Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13206>		2021-10-06 15:04:33 +00:00
..
blorp	intel/blorp: fix a compile warning about uninitialized use	2021-10-05 11:59:27 +00:00
common	intel: Add and use max_constant_urb_size_kb	2021-09-27 20:51:28 +00:00
compiler	intel/compiler: use nir_metadata_none instead of its value	2021-10-05 10:02:54 +00:00
dev	intel: Add and use max_constant_urb_size_kb	2021-09-27 20:51:28 +00:00
ds	pps: Avoid duplicate elements in with_datasources array.	2021-09-29 07:26:18 +00:00
genxml	genxml: Drop bit 27 from RENDER_SURFACE_STATE::Surface Format	2021-10-06 15:04:33 +00:00
isl	intel/isl: ASTC support was removed on Gfx12.5	2021-10-06 15:04:33 +00:00
nullhw-layer	intel/nullhw: fix build	2021-03-26 20:12:40 +00:00
perf	intel/perf: Use a char array for OA perf query data	2021-08-11 23:57:52 +00:00
tools	intel/error-decode: printout INSTDONE_GEOM register for Gfx12.5	2021-08-17 08:05:45 +00:00
vulkan	anv: Ask ISL about ASTC support	2021-10-06 15:04:33 +00:00
Makefile.perf.am	intel: Rename GEN_PERF prefix to INTEL_PERF in build files	2021-04-20 20:06:34 +00:00
meson.build	pps: Intel pps driver	2021-05-18 14:28:48 +00:00