mesa/src/amd
Rhys Perry 451e6c1b32 radv: have the null winsys set more fields
I copied stuff from ac_gpu_info.c until there were no Sienna Cichild or
Polaris10 fossil-db changes between real hardware and RADV_FORCE_FAMILY.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14126>
2021-12-14 12:11:50 +00:00
..
addrlib amd/addrlib: Use get_supported_arguments to get compiler args. 2021-11-24 07:03:54 +00:00
ci ac: change family names to uppercase in ac_get_family_name() 2021-11-23 08:07:41 +00:00
common treewide: drop mtypes/macros includes from main 2021-12-08 22:14:45 +00:00
compiler radv,aco: implement nir_op_ffma 2021-12-13 11:22:33 +00:00
llvm nir: Rename nir_get_io_vertex_index_src and include per-primitive I/O. 2021-11-16 07:46:55 +00:00
registers python: drop python2 support 2021-08-14 21:44:32 +00:00
vulkan radv: have the null winsys set more fields 2021-12-14 12:11:50 +00:00
.clang-format radv: Add clang-format for AMD code. 2021-04-10 03:31:32 +02:00
meson.build radv: Allow building when LLVM isn’t enabled 2021-10-01 10:40:18 +02:00