Bas Nieuwenhuizen 0dd0f6cf75 radv: Don't invalidate VCACHE after clear_htile_mask. ... radv_src_access_flush sets all the required flags (which doesn't include VCACHE. The flush after write is implicit. The invalidate happens for any user that needs it with the radv_dst_access_flush). Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12274>		2021-10-03 12:16:55 +00:00
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addrlib	amd/addrlib: expose CMASK address equations to drivers on GFX10+	2021-08-05 06:37:09 +00:00
ci	radv/ci: mark some tests as flaky on gfx9	2021-10-01 08:21:39 +00:00
common	ac/surface: enable DCC image stores for all displayable DCC on gfx10.3	2021-10-02 22:56:48 +00:00
compiler	radv: determine the VS output parameters in the shader info pass	2021-10-01 17:11:39 +00:00
llvm	radeonsi: implement shader-based culling for lines	2021-09-28 17:30:06 +00:00
registers	python: drop python2 support	2021-08-14 21:44:32 +00:00
vulkan	radv: Don't invalidate VCACHE after clear_htile_mask.	2021-10-03 12:16:55 +00:00
.clang-format	radv: Add clang-format for AMD code.	2021-04-10 03:31:32 +02:00
meson.build	radv: Allow building when LLVM isn’t enabled	2021-10-01 10:40:18 +02:00