mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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1e561eb1d7
It's either depth or stencil. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
119 lines
6.8 KiB
C
119 lines
6.8 KiB
C
/* Based on anv:
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* Copyright © 2015 Intel Corporation
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*
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* Copyright © 2016 Red Hat Inc.
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* Copyright © 2018 Valve Corporation
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef RADV_META_NIR_H
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#define RADV_META_NIR_H
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#include "compiler/shader_enums.h"
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#include "vulkan/vulkan_core.h"
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#include "nir_defines.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct radv_device;
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struct radeon_surf;
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enum amd_gfx_level;
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nir_builder PRINTFLIKE(3, 4)
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radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...);
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nir_shader *radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_fs_noop(struct radv_device *dev);
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nir_def *radv_meta_nir_get_global_ids(nir_builder *b, unsigned num_components);
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void radv_meta_nir_break_on_count(nir_builder *b, nir_variable *var, nir_def *count);
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nir_shader *radv_meta_nir_build_fill_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation);
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nir_shader *radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_per_invocation);
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nir_shader *radv_meta_nir_build_blit_vertex_shader(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_depth(struct radv_device *dev, enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_blit_copy_fragment_shader_stencil(struct radv_device *dev,
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enum glsl_sampler_dim tex_dim);
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nir_shader *radv_meta_nir_build_itob_compute_shader(struct radv_device *dev, bool is_3d);
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nir_shader *radv_meta_nir_build_btoi_compute_shader(struct radv_device *dev, bool is_3d);
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nir_shader *radv_meta_nir_build_itoi_compute_shader(struct radv_device *dev, bool src_3d, bool dst_3d, int samples);
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nir_shader *radv_meta_nir_build_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples);
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nir_shader *radv_meta_nir_build_cleari_96bit_compute_shader(struct radv_device *dev);
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typedef nir_def *(*radv_meta_nir_texel_fetch_build_func)(nir_builder *, uint32_t, nir_def *, bool, bool);
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nir_def *radv_meta_nir_build_blit2d_texel_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
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bool is_multisampled);
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nir_def *radv_meta_nir_build_blit2d_buffer_fetch(nir_builder *b, uint32_t binding, nir_def *tex_pos, bool is_3d,
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bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_vertex_shader(struct radv_device *device);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader(struct radv_device *device,
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radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth(struct radv_device *device,
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radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_stencil(struct radv_device *device,
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radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d, bool is_multisampled);
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nir_shader *radv_meta_nir_build_blit2d_copy_fragment_shader_depth_stencil(struct radv_device *device,
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radv_meta_nir_texel_fetch_build_func txf_func,
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const char *name, bool is_3d,
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bool is_multisampled);
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void radv_meta_nir_build_clear_color_shaders(struct radv_device *dev, struct nir_shader **out_vs,
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struct nir_shader **out_fs, uint32_t frag_output);
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void radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, struct nir_shader **out_vs,
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struct nir_shader **out_fs, bool unrestricted);
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nir_shader *radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa);
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nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, enum amd_gfx_level gfx_level,
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uint32_t gb_addr_config, const struct radeon_surf *surf);
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nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, enum amd_gfx_level gfx_level,
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uint32_t gb_addr_config, const struct radeon_surf *surf);
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nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_dcc_decompress_compute_shader(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_fmask_copy_compute_shader(struct radv_device *dev, int samples);
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nir_shader *radv_meta_nir_build_fmask_expand_compute_shader(struct radv_device *device, int samples);
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enum radv_meta_resolve_compute_type {
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RADV_META_RESOLVE_COMPUTE_NORM,
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RADV_META_RESOLVE_COMPUTE_NORM_SRGB,
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RADV_META_RESOLVE_COMPUTE_INTEGER,
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RADV_META_RESOLVE_COMPUTE_FLOAT,
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RADV_META_RESOLVE_COMPUTE_COUNT,
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};
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nir_shader *radv_meta_nir_build_resolve_compute_shader(struct radv_device *dev, bool use_fmask,
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enum radv_meta_resolve_compute_type type, int samples);
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nir_shader *radv_meta_nir_build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
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VkImageAspectFlags aspects,
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VkResolveModeFlagBits resolve_mode);
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nir_shader *radv_meta_nir_build_resolve_fragment_shader(struct radv_device *dev, bool use_fmask, bool is_integer,
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int samples);
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nir_shader *radv_meta_nir_build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples,
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VkImageAspectFlags aspects,
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VkResolveModeFlagBits resolve_mode);
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nir_shader *radv_meta_nir_build_resolve_fs(struct radv_device *dev);
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nir_shader *radv_meta_nir_build_clear_hiz_compute_shader(struct radv_device *dev, int samples);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RADV_META_NIR_H */
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