mesa/src/intel
Paulo Zanoni 1d23cf192b brw: don't mark instructions read from text assembly as compacted
I dumped assembly generated by our driver with INTEL_DEBUG=shaders,
copied and pasted it into a lua file, tried to run it with
src/intel/executor, but the disassembler started telling me some
instructions were invalid.

This happened because we print the "compacted" flag in our assembly
text, so when brw_gram.y parses our assembly flag, it sees the
"compacted" flag and sets it to the instruction by calling
add_instruction_option(). But the executor tool never sets the
BRW_ASSEMBLE_COMPACT flag when it calls brw_assemble(), so when
brw_assemble() calls dump_assembly(), which calls brw_disassbemble(),
the disassembler gets confused and prints misinterpreted instructions
and calls them invalid.

It is not the job of brw_gram.y (our text assembly parser) to mark
instructions as compacted.  Whatever is later assembling the
instruction is the entity that should decide if the instructions are
compacted or not. So in this patch we just ignore this flag.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33614>
2025-02-22 00:38:53 +00:00
..
blorp blorp: emit 3DSTATE_VF 2025-02-13 14:36:15 +00:00
ci Uprev Piglit to 04d901e49de6b650f9dceaf73220371273d87f73 2025-02-21 11:53:36 +00:00
common intel/common: fix mi_builder_test issue 2025-02-04 12:57:19 +00:00
compiler brw: don't mark instructions read from text assembly as compacted 2025-02-22 00:38:53 +00:00
decoder intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
dev intel/dev: Call intel_device_info_update_after_hwconfig() from common code 2025-02-17 20:52:31 +00:00
ds anv: add source hashes for BVH building shaders 2025-02-07 07:27:54 +00:00
executor intel: Initialize upper 32bits of drm_xe_sync.handle 2025-02-02 21:34:45 -08:00
genxml intel: Fix typos 2025-02-15 17:43:44 +00:00
isl isl: use workaround framework for Wa_1207137018 2025-01-29 12:10:13 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf intel/perf: add new perf consts to support more metrics 2025-01-16 00:01:56 +00:00
shaders intel: output a depfile with mesa_clc 2025-02-04 00:10:01 +00:00
tools intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00
vulkan nir/peephole_select: add options struct 2025-02-20 21:59:16 +00:00
vulkan_hasvk intel: switch to nir_metadata_divergence 2025-02-13 10:08:43 +00:00
meson.build intel: Add meson option -Dintel-elk 2025-01-30 00:45:59 +00:00