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On Alchemist, the FF_MODE2 documentation says that we must set the FF_MODE2 timer values for GS and HS to 224. The hardware performance tuning guide also recommends setting the TDS timer to 4. On Tigerlake, i915 applies workarounds to set the GS timer to 224 (failing to do so can cause HS/DS unit hangs), and the TDS timer to 4 (for performance). It doesn't currently apply a HS timer there, and I'm not sure if it's strictly necessary, but given that Alchemist needed it, and the other two settings matched, let's assume that it ought to match as well. Unfortunately, there has been a bug in the i915 workarounds infrastructure for non-masked context registers where writing one field of the register zeroes out all the others. So, I believe the Tigerlake TDS timer value of 4 isn't being applied correctly there, though the register is also not readable on that platform which makes it hard to verify. So, this may also speed up tessellation. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9233 Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Cc: mesa-stable Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23839> |
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